janwas
ddba0cc311
wcpu: avoid undefined shift right on 64-CPU systems (caught via assertion) filesystem: add wrename path_util: add std::wstring variants of common boost::filesystem routines This was SVN commit r8922.
103 lines
3.4 KiB
C
103 lines
3.4 KiB
C
/* Copyright (c) 2010 Wildfire Games
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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/*
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* detection of CPU and cache topology.
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* thread-safe, no explicit initialization is required.
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*/
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#ifndef INCLUDED_TOPOLOGY
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#define INCLUDED_TOPOLOGY
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/**
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* @return pointer to an array (up to os_cpu_MaxProcessors entries;
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* os_cpu_NumProcessors() of them are valid) of the processors'
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* unique, strictly monotonically increasing APIC IDs --
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* or zero if no xAPIC is present or process affinity is restricted.
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**/
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LIB_API const u8* ApicIds();
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LIB_API size_t ProcessorFromApicId(size_t apicId);
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//-----------------------------------------------------------------------------
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// cpu
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// the CPU topology, i.e. how many packages, cores and SMT units are
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// actually present and enabled, is useful for detecting SMP systems,
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// predicting performance and dimensioning thread pools.
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//
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// note: OS abstractions usually only mention "processors", which could be
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// any mix of the above.
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/**
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* @return number of *enabled* CPU packages / sockets.
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**/
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LIB_API size_t cpu_topology_NumPackages();
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/**
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* @return number of *enabled* CPU cores per package.
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* (2 on dual-core systems)
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**/
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LIB_API size_t cpu_topology_CoresPerPackage();
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/**
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* @return number of *enabled* hyperthreading units per core.
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* (2 on P4 EE)
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**/
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LIB_API size_t cpu_topology_LogicalPerCore();
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LIB_API size_t cpu_topology_PackageFromApicId(size_t apicId);
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LIB_API size_t cpu_topology_CoreFromApicId(size_t apicId);
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LIB_API size_t cpu_topology_LogicalFromApicId(size_t apicId);
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LIB_API size_t cpu_topology_ApicId(size_t idxPackage, size_t idxCore, size_t idxLogical);
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//-----------------------------------------------------------------------------
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// L2 cache
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// knowledge of the cache topology, i.e. which processors share which caches,
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// can be used to reduce contention and increase effective capacity by
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// assigning the partner processors to work on the same dataset.
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//
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// example: Intel Core2 micro-architectures feature L2 caches shared by
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// two cores.
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/**
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* @return number of distinct L2 caches.
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**/
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LIB_API size_t cache_topology_NumCaches();
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/**
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* @return L2 cache number (zero-based) to which \<processor\> belongs.
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**/
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LIB_API size_t cache_topology_CacheFromProcessor(size_t processor);
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/**
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* @return bit-mask of all processors sharing \<cache\>.
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**/
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LIB_API uintptr_t cache_topology_ProcessorMaskFromCache(size_t cache);
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#endif // #ifndef INCLUDED_TOPOLOGY
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