janwas
ffdff6888d
enable most of IA-32 specific code to be used in amd64 (resides in directory lib/sysdep/x86_x64) bits: add IsBitSet remove mem_PageSize (use os_cpu_PageSize instead) cpuid: change interface to allow gracefully supporting later subfunctions that require input parameters amd64_asm.asm: add amd64 implementation of cpuid cpu: move functions provided by OS to sysdep/os_cpu.cpp cpu topology: avoid trouble when process affinity is set by remapping processor numbers to 0..PopulationCount(processAffinity) topology.cpp: move ex-ia32 topology code here. This was SVN commit r5945.
283 lines
6.9 KiB
NASM
283 lines
6.9 KiB
NASM
; =========================================================================
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; File : ia32_asm.asm
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; Project : 0 A.D.
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; Description : optimized assembly code for IA-32. not provided as
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; : inline assembly because that's compiler-specific.
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; =========================================================================
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; license: GPL; see lib/license.txt
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%include "ia32.inc"
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; note: pure asm functions prevent inlining but also avoid redundant
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; store/loads generated by VC inline asm (ugh).
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;-------------------------------------------------------------------------------
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; CPUID support
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;-------------------------------------------------------------------------------
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; extern "C" void __cdecl ia32_asm_cpuid(x86_x64_CpuidRegs* regs);
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global sym(ia32_asm_cpuid)
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sym(ia32_asm_cpuid):
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push ebx ; (clobbered by CPUID)
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push edi ; (need a register other than eax..edx)
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mov edi, [esp+8+4] ; -> regs
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mov eax, [edi+0] ; eax (function)
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mov ecx, [edi+8] ; ecx (count)
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cpuid
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stosd
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xchg eax, ebx
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stosd
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xchg eax, ecx
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stosd
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xchg eax, edx
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stosd
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pop edi
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pop ebx
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ret
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;-------------------------------------------------------------------------------
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; lock-free support routines
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;-------------------------------------------------------------------------------
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; extern "C" void __cdecl ia32_asm_AtomicAdd(volatile intptr_t* location, intptr_t increment);
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global sym(ia32_asm_AtomicAdd)
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sym(ia32_asm_AtomicAdd):
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mov edx, [esp+4] ; location
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mov eax, [esp+8] ; increment
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db 0xf0 ; LOCK prefix
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add [edx], eax
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ret
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; notes:
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; - a 486 or later processor is required since we use CMPXCHG.
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; there's no feature flag we can check, and the ia32 code doesn't
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; bother detecting anything < Pentium, so this'll crash and burn if
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; run on 386. we could fall back to simple MOVs there (since 386 CPUs
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; aren't MP-capable), but it's not worth the trouble.
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; - nor do we bother skipping the LOCK prefix on single-processor systems.
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; the branch may be well-predicted, but difference in performance still
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; isn't expected to be enough to justify the effort.
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; extern "C" bool __cdecl ia32_asm_CAS(volatile uintptr_t* location, uintptr_t expected, uintptr_t new_value);
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global sym(ia32_asm_CAS)
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sym(ia32_asm_CAS):
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mov edx, [esp+4] ; location
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mov eax, [esp+8] ; expected
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mov ecx, [esp+12] ; new_value
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db 0xf0 ; LOCK prefix
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cmpxchg [edx], ecx
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sete al
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movzx eax, al
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ret
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;-------------------------------------------------------------------------------
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; FPU
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;-------------------------------------------------------------------------------
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[section .data]
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; to conform with the fallback implementation (a C cast), we need to
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; end up with truncate/"chop" rounding. subtracting does the trick,
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; assuming RC is the IA-32 default round-to-nearest mode.
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round_bias dd 0.4999999
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__SECT__
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; extern "C" u32 __cdecl ia32_asm_control87(u32 new_cw, u32 mask);
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global sym(ia32_asm_control87)
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sym(ia32_asm_control87):
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push eax
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fnstcw [esp]
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pop eax ; old_cw
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mov ecx, [esp+4] ; new_val
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mov edx, [esp+8] ; mask
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and ecx, edx ; new_val & mask
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not edx ; ~mask
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and eax, edx ; old_cw & ~mask
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or eax, ecx ; (old_cw & ~mask) | (new_val & mask)
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push eax ; = new_cw
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fldcw [esp]
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pop eax
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xor eax, eax ; return value
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ret
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; possible IA-32 FPU control word flags after FXAM: NAN|NORMAL|ZERO
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FP_CLASSIFY_MASK equ 0x4500
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; extern "C" size_t __cdecl ia32_asm_fpclassifyd(double d);
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global sym(ia32_asm_fpclassifyd)
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sym(ia32_asm_fpclassifyd):
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fld qword [esp+4]
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fxam
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fnstsw ax
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fstp st0
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and eax, FP_CLASSIFY_MASK
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ret
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; extern "C" size_t __cdecl ia32_asm_fpclassifyf(float f);
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global sym(ia32_asm_fpclassifyf)
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sym(ia32_asm_fpclassifyf):
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fld dword [esp+4]
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fxam
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fnstsw ax
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fstp st0
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and eax, FP_CLASSIFY_MASK
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ret
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; extern "C" float __cdecl ia32_asm_rintf(float);
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global sym(ia32_asm_rintf)
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sym(ia32_asm_rintf):
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fld dword [esp+4]
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frndint
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ret
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; extern "C" double __cdecl ia32_asm_rint(double);
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global sym(ia32_asm_rint)
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sym(ia32_asm_rint):
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fld qword [esp+4]
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frndint
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ret
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; extern "C" float __cdecl ia32_asm_fminf(float, float);
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global sym(ia32_asm_fminf)
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sym(ia32_asm_fminf):
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fld dword [esp+4]
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fld dword [esp+8]
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fcomi st0, st1
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fcmovnb st0, st1
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fxch
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fstp st0
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ret
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; extern "C" float __cdecl ia32_asm_fmaxf(float, float);
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global sym(ia32_asm_fmaxf)
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sym(ia32_asm_fmaxf):
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fld dword [esp+4]
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fld dword [esp+8]
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fcomi st0, st1
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fcmovb st0, st1
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fxch
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fstp st0
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ret
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; extern "C" i32 __cdecl ia32_asm_i32FromFloat(float f);
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global sym(ia32_asm_i32FromFloat)
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sym(ia32_asm_i32FromFloat):
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push eax
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fld dword [esp+8]
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fsub dword [round_bias]
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fistp dword [esp]
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pop eax
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ret
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; extern "C" i32 __cdecl ia32_asm_i32FromDouble(double d);
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global sym(ia32_asm_i32FromDouble)
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sym(ia32_asm_i32FromDouble):
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push eax
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fld qword [esp+8]
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fsub dword [round_bias]
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fistp dword [esp]
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pop eax
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ret
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; extern "C" i64 __cdecl ia32_asm_i64FromDouble(double d);
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global sym(ia32_asm_i64FromDouble)
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sym(ia32_asm_i64FromDouble):
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push edx
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push eax
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fld qword [esp+12]
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fsub dword [round_bias]
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fistp qword [esp]
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pop eax
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pop edx
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ret
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;-------------------------------------------------------------------------------
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; misc
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;-------------------------------------------------------------------------------
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; write the current execution state (e.g. all register values) into
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; (Win32::CONTEXT*)pcontext (defined as void* to avoid dependency).
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; optimized for size; this must be straight asm because ; extern "C"
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; is compiler-specific and compiler-generated prolog code inserted before
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; inline asm trashes EBP and ESP (unacceptable).
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; extern "C" void ia32_asm_GetCurrentContext(void* pcontext);
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global sym(ia32_asm_GetCurrentContext)
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sym(ia32_asm_GetCurrentContext):
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pushad
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pushfd
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mov edi, [esp+4+32+4] ; pcontext
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; ContextFlags
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mov eax, 0x10007 ; segs, int, control
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stosd
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; DRx and FloatSave
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; rationale: we can't access the debug registers from Ring3, and
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; the FPU save area is irrelevant, so zero them.
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xor eax, eax
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push byte 6+8+20
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pop ecx
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rep stosd
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; CONTEXT_SEGMENTS
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mov ax, gs
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stosd
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mov ax, fs
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stosd
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mov ax, es
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stosd
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mov ax, ds
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stosd
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; CONTEXT_INTEGER
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mov eax, [esp+4+32-32] ; edi
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stosd
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xchg eax, esi
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stosd
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xchg eax, ebx
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stosd
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xchg eax, edx
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stosd
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mov eax, [esp+4+32-8] ; ecx
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stosd
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mov eax, [esp+4+32-4] ; eax
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stosd
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; CONTEXT_CONTROL
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xchg eax, ebp ; ebp restored by POPAD
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stosd
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mov eax, [esp+4+32] ; return address
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sub eax, 5 ; skip CALL instruction -> call site.
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stosd
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xor eax, eax
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mov ax, cs
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stosd
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pop eax ; eflags
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stosd
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lea eax, [esp+32+4+4] ; esp
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stosd
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xor eax, eax
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mov ax, ss
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stosd
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; ExtendedRegisters
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xor ecx, ecx
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mov cl, 512/4
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rep stosd
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popad
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ret
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