forked from 0ad/0ad
fix to ia32_Generation (unfortunately, things are not as simple as querying the CPU family).
this hopefully fixes lag problems michael is seeing because rdtsc is being used on his 7-th gen athlon (which was falsely reported as 6th gen by the old version of this code) This was SVN commit r5510.
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23cae00e9e
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@ -22,10 +22,11 @@
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#include "lib/timer.h"
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#include "lib/sysdep/cpu.h"
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#if !HAVE_MS_ASM && !HAVE_GNU_ASM
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#if !MSC_VERSION && !GCC_VERSION
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#error ia32.cpp needs inline assembly support!
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#endif
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//-----------------------------------------------------------------------------
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// capability bits
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@ -118,18 +119,47 @@ static uint DetectGeneration()
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{
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uint model, family;
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DetectSignature(&model, &family);
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switch(family)
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switch(ia32_Vendor())
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{
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case 5:
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case 6:
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case 7:
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return family;
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case 0xF:
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return 8;
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default:
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debug_assert(0);
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return 0;
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case IA32_VENDOR_AMD:
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switch(family)
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{
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case 5:
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if(model < 6)
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return 5; // K5
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else
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return 6; // K6
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case 6:
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return 7; // K7 (Athlon)
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case 0xF:
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return 8; // K8 (Opteron)
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}
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break;
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case IA32_VENDOR_INTEL:
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switch(family)
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{
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case 5:
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return 5; // Pentium
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case 6:
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if(model <= 0xD)
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return 6; // Pentium Pro/II/III/M
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else
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return 8; // Core2Duo
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case 0xF:
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if(model <= 6)
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return 7; // Pentium 4/D
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}
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break;
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}
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debug_assert(0); // unknown CPU generation
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return family;
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}
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uint ia32_Generation()
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@ -609,7 +639,7 @@ uint cpu_LogicalPerCore()
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u64 ia32_rdtsc_safe()
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{
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u64 c;
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#if HAVE_MS_ASM
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#if MSC_VERSION
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__asm
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{
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cpuid
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@ -617,7 +647,7 @@ u64 ia32_rdtsc_safe()
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mov dword ptr [c], eax
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mov dword ptr [c+4], edx
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}
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#elif HAVE_GNU_ASM
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#elif GCC_VERSION
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// note: we save+restore EBX to avoid xcode complaining about a
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// "PIC register" being clobbered, whatever that means.
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__asm__ __volatile__ (
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@ -632,12 +662,12 @@ u64 ia32_rdtsc_safe()
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void ia32_DebugBreak()
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{
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#if HAVE_MS_ASM
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#if MSC_VERSION
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__asm int 3
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// note: this probably isn't necessary, since unix_debug_break
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// (SIGTRAP) is most probably available if HAVE_GNU_ASM.
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// (SIGTRAP) is most probably available if GCC_VERSION.
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// we include it for completeness, though.
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#elif HAVE_GNU_ASM
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#elif GCC_VERSION
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__asm__ __volatile__ ("int $3");
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#endif
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}
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@ -648,9 +678,9 @@ void cpu_MemoryFence()
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{
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// Pentium IV
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if(ia32_cap(IA32_CAP_SSE2))
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#if HAVE_MS_ASM
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#if MSC_VERSION
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__asm mfence
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#elif HAVE_GNU_ASM
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#elif GCC_VERSION
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__asm__ __volatile__ ("mfence");
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#endif
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}
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