665 lines
17 KiB
NASM
665 lines
17 KiB
NASM
; set section attributes
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section .data data align=32 use32
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section .bss bss align=16 use32
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section .text code align=64 use32
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; activate .text (needs to be separate because __SECT__ will otherwise
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; complain that the above definition is redeclaring attributes)
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section .text
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; Usage:
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; use sym(ia32_cap) instead of _ia32_cap - on relevant platforms, sym() will add
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; the underlines automagically, on others it won't
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%ifdef DONT_USE_UNDERLINE
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%define sym(a) a
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%else
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%define sym(a) _ %+ a
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%endif
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;-------------------------------------------------------------------------------
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; fast general memcpy
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;-------------------------------------------------------------------------------
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; drop-in replacement for libc memcpy(). only requires CPU support for
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; MMX (by now universal). highly optimized for Athlon and Pentium III
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; microarchitectures; significantly outperforms VC7.1 memcpy and memcpy_amd.
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; for details, see accompanying article.
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; if transfer size is at least this much,
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; .. it's too big for L1. use non-temporal instructions.
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UC_THRESHOLD equ 64*1024
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; .. it also blows L2. pull chunks into L1 ("block prefetch").
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BP_THRESHOLD equ 256*1024
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; maximum that can be copied by IC_TINY.
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IC_TINY_MAX equ 63
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; size of one block prefetch chunk.
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BP_SIZE equ 8*1024
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;------------------------------------------------------------------------------
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; [p3] replicating this instead of jumping to it from tailN
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; saves 1 clock and costs (7-2)*2 bytes code.
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%macro EPILOG 0
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pop esi
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pop edi
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mov eax, [esp+4] ; return dst
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ret
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%endm
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align 64
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tail1:
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mov al, [esi+ecx*4]
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mov [edi+ecx*4], al
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align 4
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tail0:
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EPILOG
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align 8
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tail3:
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; [p3] 2 reads followed by 2 writes is better than
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; R/W interleaved and RRR/WWW
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mov al, [esi+ecx*4+2]
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mov [edi+ecx*4+2], al
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; already aligned to 8 due to above code
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tail2:
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mov al, [esi+ecx*4]
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mov dl, [esi+ecx*4+1]
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mov [edi+ecx*4], al
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mov [edi+ecx*4+1], dl
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EPILOG
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[section .data]
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align 16
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tail_table dd tail0, tail1, tail2, tail3
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__SECT__
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; 15x unrolled copy loop - transfers DWORDs backwards.
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; indexed via table of 8-bit offsets.
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; rationale:
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; - [p3] backwards vs. forwards makes no difference.
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; - MOV is faster than MOVSD.
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; - index table is needed because calculating end-6*i is slower than
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; a LUT and we wouldn't want to expand entries to 8 bytes
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; (that'd increase code footprint by 30 bytes)
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; - a byte index accessed via MOVZX is better due to less dcache usage.
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; - only unrolling 8x and 'reentering' the loop is possible but
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; slower due to fiddling with esi/ecx.
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align 64
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unrolled_copy_code_start:
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%assign i 15
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%rep 14 ; 15 entries, 1 base case handled below
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uc_ %+ i:
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mov eax, [esi+i*4-4]
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mov [edi+i*4-4], eax
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%assign i i-1
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%endrep
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; base case: no displacement needed; skip it so that code will
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; be aligned to 8 bytes after this.
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uc_1:
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mov eax, [esi]
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mov [edi], eax
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uc_0:
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jmp [tail_table+edx*4]
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[section .data]
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align 32
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unrolled_copy_index_table:
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%assign i 0
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%rep 16
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db (uc_ %+ i) - unrolled_copy_code_start
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%assign i i+1
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%endrep
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__SECT__
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;------------------------------------------------------------------------------
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; tiny copy - handles all cases smaller than IC_MOVQ's 64 byte lower limit.
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; > edx = number of bytes (< IC_TINY_MAX)
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; < does not return.
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; x eax, ecx, edx
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%macro IC_TINY 0
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mov ecx, edx
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shr ecx, 2
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; calculating this address isn't possible due to skipping displacement on uc1;
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; even so, it'd require calculating -6*ecx, which is slower than LUT.
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movzx eax, byte [unrolled_copy_index_table+ecx]
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and edx, byte 3
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add eax, unrolled_copy_code_start
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jmp eax
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; never reached! the unrolled loop jumps into tailN, which
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; then returns from the memcpy function.
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%endm
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;------------------------------------------------------------------------------
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; align destination address to multiple of 8. important for large transfers,
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; but doesn't affect the tiny technique.
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; > esi, edi -> buffers (updated)
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; > ecx, edx = transfer size (updated)
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; x eax
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%macro IC_ALIGN 0
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mov eax, edi
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and eax, byte 7 ; eax = # misaligned bytes
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jz already_aligned ; early out
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lea eax, [align_table_start+eax*2]
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jmp eax
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; [p3] this is no slower than a table of mov and much smaller/simpler
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align 8
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align_table_start:
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%rep 8
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dec ecx
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movsb
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%endrep
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mov edx, ecx
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already_aligned:
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%endm
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;------------------------------------------------------------------------------
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; MMX MOVQ technique. used for in-cache transfers of 64B..64*KiB.
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; must run on all CPUs, i.e. cannot use the SSE prefetchnta instruction.
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; > ecx = -number_of_bytes (multiple of 64)
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; > esi, esi point to end of the buffer, i.e. &last_qword+8.
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; < ecx = 0
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; x
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%macro IC_MOVQ 0
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align 16
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%%loop:
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; notes:
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; - we can't use prefetch here - this codepath must support all CPUs.
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; [p3] that makes us 5..15% slower on 1KiB..4KiB transfers.
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; - [p3] simple addressing without +ecx is 3.5% faster.
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; - difference between RR/WW/RR/WW and R..R/W..W:
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; [p3] none (if simple addressing)
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; [axp] interleaved is better (with +ecx addressing)
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; - enough time elapses between first and third pair of reads that we
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; could reuse MM0. there is no performance gain either way and
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; differing displacements make code compression futile anyway, so
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; we'll just use MM4..7 for clarity.
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movq mm0, [esi+ecx]
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movq mm1, [esi+ecx+8]
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movq [edi+ecx], mm0
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movq [edi+ecx+8], mm1
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movq mm2, [esi+ecx+16]
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movq mm3, [esi+ecx+24]
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movq [edi+ecx+16], mm2
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movq [edi+ecx+24], mm3
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movq mm4, [esi+ecx+32]
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movq mm5, [esi+ecx+40]
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movq [edi+ecx+32], mm4
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movq [edi+ecx+40], mm5
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movq mm6, [esi+ecx+48]
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movq mm7, [esi+ecx+56]
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movq [edi+ecx+48], mm6
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movq [edi+ecx+56], mm7
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add ecx, byte 64
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jnz %%loop
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%endm
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;------------------------------------------------------------------------------
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; SSE MOVNTQ technique. used for transfers that do not fit in L1,
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; i.e. 64KiB..192KiB. requires Pentium III or Athlon; caller checks for this.
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; > ecx = -number_of_bytes (multiple of 64)
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; > esi, esi point to end of the buffer, i.e. &last_qword+8.
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; < ecx = 0
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; x
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%macro UC_MOVNTQ 0
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align 16
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%%loop:
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; notes:
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; - the AMD optimization manual recommends prefetch distances according to
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; (200*BytesPerIter/ClocksPerIter+192), which comes out to ~560 here.
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; [p3] rounding down to 512 bytes makes for significant gains.
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; - [p3] complex addressing with ecx is 1% faster than adding to esi/edi.
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prefetchnta [esi+ecx+512]
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movq mm0, [esi+ecx]
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movq mm1, [esi+ecx+8]
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movq mm2, [esi+ecx+16]
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movq mm3, [esi+ecx+24]
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movq mm4, [esi+ecx+32]
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movq mm5, [esi+ecx+40]
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movq mm6, [esi+ecx+48]
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movq mm7, [esi+ecx+56]
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movntq [edi+ecx], mm0
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movntq [edi+ecx+8], mm1
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movntq [edi+ecx+16], mm2
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movntq [edi+ecx+24], mm3
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movntq [edi+ecx+32], mm4
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movntq [edi+ecx+40], mm5
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movntq [edi+ecx+48], mm6
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movntq [edi+ecx+56], mm7
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add ecx, byte 64
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jnz %%loop
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%endm
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;------------------------------------------------------------------------------
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; block prefetch technique. used for transfers that do not fit in L2,
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; i.e. > 192KiB. requires Pentium III or Athlon; caller checks for this.
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; for theory behind this, see article.
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; > ecx = -number_of_bytes (multiple of 64, <= -BP_SIZE)
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; > esi, esi point to end of the buffer, i.e. &last_qword+8.
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; < ecx = -remaining_bytes (multiple of 64, > -BP_SIZE)
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; < eax = 0
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%macro UC_BP_MOVNTQ 0
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push edx
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align 4
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%%prefetch_and_copy_chunk:
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; pull chunk into cache by touching each cache line
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; (in reverse order to prevent HW prefetches)
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mov eax, BP_SIZE/128 ; # iterations
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add esi, BP_SIZE
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align 16
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%%prefetch_loop:
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mov edx, [esi+ecx-64]
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mov edx, [esi+ecx-128]
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add esi, byte -128
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dec eax
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jnz %%prefetch_loop
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; copy chunk in 64 byte pieces
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mov eax, BP_SIZE/64 ; # iterations (> signed 8 bit)
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align 16
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%%copy_loop:
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movq mm0, [esi+ecx]
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movq mm1, [esi+ecx+8]
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movq mm2, [esi+ecx+16]
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movq mm3, [esi+ecx+24]
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movq mm4, [esi+ecx+32]
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movq mm5, [esi+ecx+40]
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movq mm6, [esi+ecx+48]
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movq mm7, [esi+ecx+56]
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movntq [edi+ecx], mm0
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movntq [edi+ecx+8], mm1
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movntq [edi+ecx+16], mm2
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movntq [edi+ecx+24], mm3
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movntq [edi+ecx+32], mm4
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movntq [edi+ecx+40], mm5
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movntq [edi+ecx+48], mm6
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movntq [edi+ecx+56], mm7
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add ecx, byte 64
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dec eax
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jnz %%copy_loop
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; if enough data left, process next chunk
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cmp ecx, -BP_SIZE
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jle %%prefetch_and_copy_chunk
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pop edx
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%endm
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;------------------------------------------------------------------------------
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; void* __declspec(naked) ia32_memcpy(void* dst, const void* src, size_t nbytes)
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; drop-in replacement for libc memcpy() (returns dst)
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global sym(ia32_memcpy)
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align 64
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sym(ia32_memcpy):
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push edi
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push esi
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mov ecx, [esp+8+4+8] ; nbytes
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mov edi, [esp+8+4+0] ; dst
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mov esi, [esp+8+4+4] ; src
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mov edx, ecx
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cmp ecx, byte IC_TINY_MAX
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ja choose_larger_method
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ic_tiny:
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IC_TINY
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; never reached - IC_TINY contains memcpy function epilog code
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choose_larger_method:
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IC_ALIGN
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; setup:
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; eax = number of 64 byte chunks, or 0 if CPU doesn't support SSE.
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; used to choose copy technique.
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; ecx = -number_of_bytes, multiple of 64. we jump to ic_tiny if
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; there's not enough left for a single 64 byte chunk, which can
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; happen on unaligned 64..71 byte transfers due to IC_ALIGN.
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; edx = number of remainder bytes after qwords have been copied;
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; will be handled by IC_TINY.
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; esi and edi point to end of the respective buffers (more precisely,
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; to buffer_start-ecx). this together with the ecx convention means
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; we only need one loop counter (instead of having to advance
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; that and esi/edi).
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; this mask is applied to the transfer size. the 2 specialized copy techniques
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; that use SSE are jumped to if size is greater than a threshold.
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; we simply set the requested transfer size to 0 if the CPU doesn't
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; support SSE so that those are never reached (done by masking with this).
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extern sym(ia32_memcpy_size_mask)
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mov eax, [sym(ia32_memcpy_size_mask)]
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and ecx, byte ~IC_TINY_MAX
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jz ic_tiny ; < 64 bytes left (due to IC_ALIGN)
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add esi, ecx
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add edi, ecx
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and edx, byte IC_TINY_MAX
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and eax, ecx
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neg ecx
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cmp eax, BP_THRESHOLD
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jae near uc_bp_movntq
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cmp eax, UC_THRESHOLD
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jae uc_movntq
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ic_movq:
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IC_MOVQ
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emms
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jmp ic_tiny
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uc_movntq:
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UC_MOVNTQ
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sfence
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emms
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jmp ic_tiny
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uc_bp_movntq:
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UC_BP_MOVNTQ
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sfence
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cmp ecx, byte -(IC_TINY_MAX+1)
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jle ic_movq
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emms
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jmp ic_tiny
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;-------------------------------------------------------------------------------
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; CPUID support
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;-------------------------------------------------------------------------------
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[section .data]
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; these are actually max_func+1, i.e. the first invalid value.
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; the idea here is to avoid a separate cpuid_available flag;
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; using signed values doesn't work because ext_funcs are >= 0x80000000.
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max_func dd 0
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max_ext_func dd 0
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__SECT__
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; extern "C" bool __cdecl ia32_cpuid(u32 func, u32* regs)
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global sym(ia32_cpuid)
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sym(ia32_cpuid):
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push ebx
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push edi
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mov ecx, [esp+8+4+0] ; func
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mov edi, [esp+8+4+4] ; -> regs
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; compare against max supported func and fail if above
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xor eax, eax ; return value on failure
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test ecx, ecx
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mov edx, [max_ext_func]
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js .is_ext_func
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mov edx, [max_func]
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.is_ext_func:
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cmp ecx, edx
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jae .ret ; (see max_func decl)
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; issue CPUID and store result registers in array
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mov eax, ecx
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cpuid
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stosd
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xchg eax, ebx
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stosd
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xchg eax, ecx
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stosd
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xchg eax, edx
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stosd
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; success
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xor eax, eax
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inc eax
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.ret:
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pop edi
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pop ebx
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ret
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;-------------------------------------------------------------------------------
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; lock-free support routines
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;-------------------------------------------------------------------------------
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extern sym(cpus)
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; extern "C" void __cdecl atomic_add(intptr_t* location, intptr_t increment);
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global sym(atomic_add)
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sym(atomic_add):
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cmp byte [sym(cpus)], 1
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mov edx, [esp+4] ; location
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mov eax, [esp+8] ; increment
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je .no_lock
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db 0xf0 ; LOCK prefix
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.no_lock:
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add [edx], eax
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ret
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; notes:
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; - this is called via CAS macro, which silently casts its inputs for
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; convenience. mixing up the <expected> and <location> parameters would
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; go unnoticed; we therefore perform a basic sanity check on <location> and
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; raise a warning if it is invalid.
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; - a 486 or later processor is required since we use CMPXCHG.
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; there's no feature flag we can check, and the ia32 code doesn't
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; bother detecting anything < Pentium, so this'll crash and burn if
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; run on 386. we could fall back to simple MOVs there (since 386 CPUs
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; aren't MP-capable), but it's not worth the trouble.
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; extern "C" __declspec(naked) bool __cdecl CAS_(uintptr_t* location, uintptr_t expected, uintptr_t new_value);
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global sym(CAS_)
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sym(CAS_):
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cmp byte [sym(cpus)], 1
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mov eax, [esp+8] ; expected
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mov edx, [esp+4] ; location
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cmp edx, 0x10000 ; .. valid pointer?
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jb .invalid_location ; no - raise warning
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mov ecx, [esp+12] ; new_value
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je .no_lock
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db 0xf0 ; LOCK prefix
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.no_lock:
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cmpxchg [edx], ecx
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sete al
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movzx eax, al
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ret
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; NOTE: nasm 0.98.39 doesn't support generating debug info for win32
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; output format. that means this code may be misattributed to other
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; functions, which makes tracking it down very difficult.
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; we therefore raise an "Invalid Opcode" exception, which is rather distinct.
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.invalid_location:
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ud2
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;-------------------------------------------------------------------------------
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; misc
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;-------------------------------------------------------------------------------
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; extern "C" uint __cdecl ia32_control87(uint new_cw, uint mask)
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global sym(ia32_control87)
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sym(ia32_control87):
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push eax
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fnstcw [esp]
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pop eax ; old_cw
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mov ecx, [esp+4] ; new_val
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mov edx, [esp+8] ; mask
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and ecx, edx ; new_val & mask
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not edx ; ~mask
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and eax, edx ; old_cw & ~mask
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or eax, ecx ; (old_cw & ~mask) | (new_val & mask)
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push eax ; = new_cw
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fldcw [esp]
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pop eax
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xor eax, eax ; return value
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ret
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; write the current execution state (e.g. all register values) into
|
|
; (Win32::CONTEXT*)pcontext (defined as void* to avoid dependency).
|
|
; optimized for size; this must be straight asm because __declspec(naked)
|
|
; is compiler-specific and compiler-generated prolog code inserted before
|
|
; inline asm trashes EBP and ESP (unacceptable).
|
|
; extern "C" void ia32_get_current_context(void* pcontext)
|
|
global sym(ia32_get_current_context)
|
|
sym(ia32_get_current_context):
|
|
pushad
|
|
pushfd
|
|
mov edi, [esp+4+32+4] ; pcontext
|
|
|
|
; ContextFlags
|
|
mov eax, 0x10007 ; segs, int, control
|
|
stosd
|
|
|
|
; DRx and FloatSave
|
|
; rationale: we can't access the debug registers from Ring3, and
|
|
; the FPU save area is irrelevant, so zero them.
|
|
xor eax, eax
|
|
push byte 6+8+20
|
|
pop ecx
|
|
rep stosd
|
|
|
|
; CONTEXT_SEGMENTS
|
|
mov ax, gs
|
|
stosd
|
|
mov ax, fs
|
|
stosd
|
|
mov ax, es
|
|
stosd
|
|
mov ax, ds
|
|
stosd
|
|
|
|
; CONTEXT_INTEGER
|
|
mov eax, [esp+4+32-32] ; edi
|
|
stosd
|
|
xchg eax, esi
|
|
stosd
|
|
xchg eax, ebx
|
|
stosd
|
|
xchg eax, edx
|
|
stosd
|
|
mov eax, [esp+4+32-8] ; ecx
|
|
stosd
|
|
mov eax, [esp+4+32-4] ; eax
|
|
stosd
|
|
|
|
; CONTEXT_CONTROL
|
|
xchg eax, ebp ; ebp restored by POPAD
|
|
stosd
|
|
mov eax, [esp+4+32] ; return address
|
|
sub eax, 5 ; skip CALL instruction -> call site.
|
|
stosd
|
|
xor eax, eax
|
|
mov ax, cs
|
|
stosd
|
|
pop eax ; eflags
|
|
stosd
|
|
lea eax, [esp+32+4+4] ; esp
|
|
stosd
|
|
xor eax, eax
|
|
mov ax, ss
|
|
stosd
|
|
|
|
; ExtendedRegisters
|
|
xor ecx, ecx
|
|
mov cl, 512/4
|
|
rep stosd
|
|
|
|
popad
|
|
ret
|
|
|
|
|
|
;-------------------------------------------------------------------------------
|
|
; init
|
|
;-------------------------------------------------------------------------------
|
|
|
|
; extern "C" bool __cdecl ia32_asm_init()
|
|
global sym(ia32_asm_init)
|
|
sym(ia32_asm_init):
|
|
push ebx
|
|
|
|
; check if CPUID is supported
|
|
pushfd
|
|
or byte [esp+2], 32
|
|
popfd
|
|
pushfd
|
|
pop eax
|
|
xor edx, edx
|
|
shr eax, 22 ; bit 21 toggled?
|
|
jnc .no_cpuid
|
|
|
|
; determine max supported CPUID function
|
|
xor eax, eax
|
|
cpuid
|
|
inc eax ; (see max_func decl)
|
|
mov [max_func], eax
|
|
mov eax, 0x80000000
|
|
cpuid
|
|
inc eax ; (see max_func decl)
|
|
mov [max_ext_func], eax
|
|
.no_cpuid:
|
|
|
|
pop ebx
|
|
ret
|
|
|
|
|
|
;-------------------------------------------------------------------------------
|
|
; Color conversion (SSE)
|
|
;-------------------------------------------------------------------------------
|
|
|
|
; extern "C" u32 ConvertRGBColorTo4ub(const RGBColor& color)
|
|
[section .data]
|
|
align 16
|
|
zero:
|
|
dd 0.0
|
|
twofivefive:
|
|
dd 255.0
|
|
|
|
|
|
__SECT__
|
|
align 16
|
|
global sym(sse_ConvertRGBColorTo4ub)
|
|
sym(sse_ConvertRGBColorTo4ub):
|
|
mov eax, [esp+4]
|
|
|
|
; xmm0, 1, 2 = R, G, B
|
|
movss xmm4, [zero]
|
|
movss xmm0, [eax+8]
|
|
movss xmm1, [eax+4]
|
|
movss xmm2, [eax]
|
|
movss xmm5, [twofivefive]
|
|
|
|
; C = min(255, 255*max(C, 0)) ( == clamp(255*C, 0, 255) )
|
|
maxss xmm0, xmm4
|
|
maxss xmm1, xmm4
|
|
maxss xmm2, xmm4
|
|
mulss xmm0, xmm5
|
|
mulss xmm1, xmm5
|
|
mulss xmm2, xmm5
|
|
minss xmm0, xmm5
|
|
minss xmm1, xmm5
|
|
minss xmm2, xmm5
|
|
|
|
; convert to integer and combine channels using bit logic
|
|
cvtss2si eax, xmm0
|
|
cvtss2si ecx, xmm1
|
|
cvtss2si edx, xmm2
|
|
shl eax, 16
|
|
shl ecx, 8
|
|
or eax, 0xff000000
|
|
or edx, ecx
|
|
or eax, edx
|
|
|
|
ret
|