olsner
d0f7cb015c
- Ported lockless code to gcc inline assembly - A few new net messages (gather, attack, add waypoint) - Support for new messages in network->entity order converter - Implemented rudimentary JS interface for Interaction - issueCommand JS API, connected to the network - Removed Interaction stuff now replaced by JS - And something in there should probably break VS builds :P This was SVN commit r2316.
80 lines
1.9 KiB
C
Executable File
80 lines
1.9 KiB
C
Executable File
// IA-32 (x86) specific code
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// Copyright (c) 2003 Jan Wassenberg
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//
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// This program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as
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// published by the Free Software Foundation; either version 2 of the
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// License, or (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but
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// WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// Contact info:
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// Jan.Wassenberg@stud.uni-karlsruhe.de
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// http://www.stud.uni-karlsruhe.de/~urkt/
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#ifndef IA32_H
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#define IA32_H
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#if !(defined(__GNUC__) && defined(i386)) && !defined(_M_IX86)
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#error "including ia32.h without _M_IX86 (or both __GNUC__ and i386) defined"
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#endif
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#include "lib/types.h"
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extern double _ceil(double);
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extern u64 rdtsc(void);
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#ifndef _MCW_PC
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#define _MCW_PC 0x0300 // Precision Control
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#endif
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#ifndef _PC_24
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#define _PC_24 0x0000 // 24 bits
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#endif
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#define _control87 ia32_control87
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extern uint ia32_control87(uint new_cw, uint mask);
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extern void ia32_debug_break(void);
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// CPU caps (128 bits)
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// do not change the order! (breaks cpuid())
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enum CpuCap
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{
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// standard (ecx)
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// currently only defined by Intel
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SSE3 = 0+0, // Streaming SIMD Extensions 3
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EST = 0+7, // Enhanced Speedstep Technology
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// standard (edx)
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TSC = 32+4, // TimeStamp Counter
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CMOV = 32+15, // Conditional MOVe
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MMX = 32+23, // MultiMedia eXtensions
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SSE = 32+25, // Streaming SIMD Extensions
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SSE2 = 32+26, // Streaming SIMD Extensions 2
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HT = 32+28, // HyperThreading
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// extended (ecx)
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// extended (edx)
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// currently only defined by AMD
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MP = 96+19, // MultiProcessing capable; reserved on AMD64
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_3DNOW_PRO = 96+30,
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_3DNOW = 96+31
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};
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extern bool ia32_cap(CpuCap cap);
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extern void ia32_get_cpu_info(void);
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#endif // #ifndef IA32_H
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