janwas
12ac1deebd
ia32: add note on when ia32_ApicId fails; support detecting/guessing processor topology from number of "processors" (hopefully fixes warning on Philip's PIII system) This was SVN commit r5209.
202 lines
5.3 KiB
C
202 lines
5.3 KiB
C
/**
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* =========================================================================
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* File : ia32.h
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* Project : 0 A.D.
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* Description : C++ and inline asm implementations of IA-32 functions
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* =========================================================================
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*/
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// license: GPL; see lib/license.txt
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#ifndef INCLUDED_IA32
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#define INCLUDED_IA32
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#if !CPU_IA32
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#error "including ia32.h without CPU_IA32=1"
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#endif
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#include "ia32_asm.h"
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#include "ia32_memcpy.h"
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/**
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* must be called before any of the following functions.
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**/
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extern void ia32_Init();
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extern void ia32_Shutdown();
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/**
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* CPU vendor.
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* (this is exposed because some CPUID functions are vendor-specific.)
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* (an enum is easier to compare than the original string values.)
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**/
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enum Ia32Vendor
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{
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IA32_VENDOR_UNKNOWN,
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IA32_VENDOR_INTEL,
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IA32_VENDOR_AMD,
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};
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extern Ia32Vendor ia32_Vendor();
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/**
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* @return the colloquial processor generation
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* (6 = Pentium II / K6, 7 = Pentium III / Athlon, 8 = Opteron)
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**/
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extern uint ia32_Generation();
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/**
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* bit indices of CPU capability flags (128 bits).
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* values are defined by IA-32 CPUID feature flags - do not change!
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**/
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enum IA32Cap
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{
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// standard (ecx) - currently only defined by Intel
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IA32_CAP_SSE3 = 0+0, // Streaming SIMD Extensions 3
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IA32_CAP_EST = 0+7, // Enhanced Speedstep Technology
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// standard (edx)
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IA32_CAP_FPU = 32+0, // Floating Point Unit
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IA32_CAP_TSC = 32+4, // TimeStamp Counter
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IA32_CAP_CMOV = 32+15, // Conditional MOVe
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IA32_CAP_TM_SCC = 32+22, // Thermal Monitoring and Software Controlled Clock
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IA32_CAP_MMX = 32+23, // MultiMedia eXtensions
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IA32_CAP_SSE = 32+25, // Streaming SIMD Extensions
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IA32_CAP_SSE2 = 32+26, // Streaming SIMD Extensions 2
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IA32_CAP_HT = 32+28, // HyperThreading
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// extended (ecx)
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IA32_CAP_AMD_CMP_LEGACY = 64+1, // N-core and IA32_CAP_HT is falsely set
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// extended (edx)
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IA32_CAP_AMD_MP = 96+19, // MultiProcessing capable; reserved on AMD64
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IA32_CAP_AMD_MMX_EXT = 96+22,
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IA32_CAP_AMD_3DNOW_PRO = 96+30,
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IA32_CAP_AMD_3DNOW = 96+31
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};
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/**
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* @return whether the CPU supports the indicated IA32Cap / feature flag.
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**/
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extern bool ia32_cap(IA32Cap cap);
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// CPU detection
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/**
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* @return string identifying the CPU (usually a cleaned-up version of the
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* brand string)
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**/
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extern const char* ia32_IdentifierString();
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/**
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* @return the cached result of a precise measurement of the
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* CPU frequency.
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**/
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extern double ia32_ClockFrequency();
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/**
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* @return number of *enabled* CPU packages / sockets.
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**/
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extern uint ia32_NumPackages();
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/**
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* @return number of *enabled* CPU cores per package.
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* (2 on dual-core systems)
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**/
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extern uint ia32_CoresPerPackage();
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/**
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* @return number of *enabled* hyperthreading units per core.
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* (2 on P4 EE)
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**/
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extern uint ia32_LogicalPerCore();
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//-----------------------------------------------------------------------------
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// stateless
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/**
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* @return APIC ID of the currently executing processor.
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*
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* the implementation uses CPUID.1 and only works on >= 8th generation CPUs;
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* (P4/Athlon XP); otherwise it returns 0. the alternative of accessing the
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* APIC mmio registers is not feasible - mahaf_MapPhysicalMemory only works
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* reliably on WinXP. also, the OS already has the APIC registers mapped and
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* in constant use, and we don't want to interfere.
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**/
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extern uint ia32_ApicId();
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/**
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* check if there is an IA-32 CALL instruction right before ret_addr.
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* @return INFO::OK if so and ERR::FAIL if not.
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*
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* also attempts to determine the call target. if that is possible
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* (directly addressed relative or indirect jumps), it is stored in
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* target, which is otherwise 0.
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*
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* this function is used for walking the call stack.
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**/
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extern LibError ia32_GetCallTarget(void* ret_addr, void** target);
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/// safe but slow inline-asm version
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extern u64 ia32_rdtsc_safe(void);
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/**
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* @return the current value of the TimeStampCounter (a counter of
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* CPU cycles since power-on, which is useful for high-resolution timing
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* but potentially differs between multiple CPUs)
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**/
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extern u64 ia32_rdtsc(); // only for CppDoc's benefit
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#if CONFIG_RETURN64_EDX_EAX
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# define ia32_rdtsc ia32_asm_rdtsc_edx_eax
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#else
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# define ia32_rdtsc ia32_rdtsc_safe
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#endif
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/**
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* trigger a breakpoint inside this function when it is called.
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**/
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extern void ia32_DebugBreak(void);
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// implementations of the cpu.h interface
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/// see cpu_MemoryFence
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extern void ia32_MemoryFence();
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// see cpu_Serialize
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extern void ia32_Serialize();
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/// fpclassify return values
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#define IA32_FP_NAN 0x0100
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#define IA32_FP_NORMAL 0x0400
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#define IA32_FP_INFINITE (IA32_FP_NAN | IA32_FP_NORMAL)
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#define IA32_FP_ZERO 0x4000
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#define IA32_FP_SUBNORMAL (IA32_FP_NORMAL | IA32_FP_ZERO)
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// FPU control word (for ia32_asm_control87)
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// .. Precision Control:
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#define IA32_MCW_PC 0x0300
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#define IA32_PC_24 0x0000
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// .. Rounding Control:
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#define IA32_MCW_RC 0x0C00
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#define IA32_RC_NEAR 0x0000
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#define IA32_RC_DOWN 0x0400
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#define IA32_RC_UP 0x0800
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#define IA32_RC_CHOP 0x0C00
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// .. Exception Mask:
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#define IA32_MCW_EM 0x003f
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#define IA32_EM_INVALID BIT(0)
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#define IA32_EM_DENORMAL BIT(1)
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#define IA32_EM_ZERODIVIDE BIT(2)
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#define IA32_EM_OVERFLOW BIT(3)
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#define IA32_EM_UNDERFLOW BIT(4)
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#define IA32_EM_INEXACT BIT(5)
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#endif // #ifndef INCLUDED_IA32
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