forked from 0ad/0ad
Adds L4 cache detection for some new Haswell CPUs, fixes #2074
This was SVN commit r13736.
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@ -1,4 +1,4 @@
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/* Copyright (c) 2011 Wildfire Games
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/* Copyright (c) 2013 Wildfire Games
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*
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* a copy of this software and associated documentation files (the
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@ -37,7 +37,7 @@ struct Cache // POD (may be used before static constructors)
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// note: further values are "reserved"
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// note: further values are "reserved"
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};
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};
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static const size_t maxLevels = 3;
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static const size_t maxLevels = 4;
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static const size_t fullyAssociative = 0xFF; // (CPUID.4 definition)
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static const size_t fullyAssociative = 0xFF; // (CPUID.4 definition)
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@ -125,9 +125,11 @@ enum IdxCache
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L1D = 1,
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L1D = 1,
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L2D,
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L2D,
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L3D,
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L3D,
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L4D,
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L1I,
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L1I,
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L2I,
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L2I,
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L3I,
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L3I,
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L4I,
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TLB
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TLB
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};
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};
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