forked from 0ad/0ad
noted while checking MSR prerequisites that the previous HasNehalem is inaccurate. PLATFORM_INFO is also supported by newer processors (e.g. Sandy Bridge), whereas UNCORE_* are tied to Nehalem and Westmere => split up HasNehalem into HasPlatformInfo and HasUncore. (the latter has been replaced by a "system agent" in newer designs)
refs #754 This was SVN commit r9136.
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@ -63,7 +63,7 @@ bool HasEnergyPerfBias()
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}
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bool HasNehalem()
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bool HasPlatformInfo()
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{
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if(x86_x64_Vendor() != X86_X64_VENDOR_INTEL)
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return false;
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@ -73,13 +73,49 @@ bool HasNehalem()
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switch(x86_x64_Model())
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{
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// Nehalem (documented in 253669-035US B.4.1)
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// Xeon 5500 / i7 (section B.4 in 253669-037US)
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case 0x1A: // Bloomfield, Gainstown
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case 0x1E: // Clarksfield, Lynnfield, Jasper Forest
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case 0x1F:
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return true;
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// Westmere (documented in 253669-035US B.5)
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// Xeon 7500 (section B.4.2)
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case 0x2E:
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return true;
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// Xeon 5600 / Westmere (section B.5)
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case 0x25: // Clarkdale, Arrandale
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case 0x2C: // Gulftown
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return true;
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// Xeon 2xxx / Sandy Bridge (section B.6)
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case 0x2A:
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case 0x2D:
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return true;
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default:
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return false;
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}
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}
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bool HasUncore()
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{
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if(x86_x64_Vendor() != X86_X64_VENDOR_INTEL)
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return false;
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if(x86_x64_Family() != 6)
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return false;
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switch(x86_x64_Model())
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{
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// Xeon 5500 / i7 (section B.4.1 in 253669-037US)
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case 0x1A: // Bloomfield, Gainstown
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case 0x1E: // Clarksfield, Lynnfield, Jasper Forest
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case 0x1F:
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return true;
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// Xeon 5600 / Westmere (section B.5)
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case 0x25: // Clarkdale, Arrandale
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case 0x2C: // Gulftown
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return true;
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@ -44,19 +44,22 @@ enum ModelSpecificRegisters
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IA32_PERF_GLOBAL_CTRL = 0x38F,
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IA32_PERF_GLOBAL_OVF_CTRL = 0x390,
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// Nehalem (requires HasNehalem)
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NHM_PLATFORM_INFO = 0x0CE,
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NHM_UNCORE_PERF_GLOBAL_CTRL = 0x391,
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NHM_UNCORE_PERF_GLOBAL_STATUS = 0x392,
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NHM_UNCORE_PERF_GLOBAL_OVF_CTRL = 0x393,
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NHM_UNCORE_PMC0 = 0x3B0,
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NHM_UNCORE_PERFEVTSEL0 = 0x3C0
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// Nehalem and later
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PLATFORM_INFO = 0x0CE, // requires HasPlatformInfo
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// Nehalem, Westmere (requires HasUncore)
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UNCORE_PERF_GLOBAL_CTRL = 0x391,
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UNCORE_PERF_GLOBAL_STATUS = 0x392,
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UNCORE_PERF_GLOBAL_OVF_CTRL = 0x393,
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UNCORE_PMC0 = 0x3B0,
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UNCORE_PERFEVTSEL0 = 0x3C0
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};
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LIB_API bool IsAccessible();
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LIB_API bool HasEnergyPerfBias();
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LIB_API bool HasNehalem();
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LIB_API bool HasPlatformInfo();
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LIB_API bool HasUncore();
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LIB_API u64 Read(u64 reg);
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LIB_API void Write(u64 reg, u64 value);
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@ -222,9 +222,9 @@ public:
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// clock is subject to thermal drift and would require continual
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// recalibration anyway.
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#if ARCH_X86_X64
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if(MSR::IsAccessible() && MSR::HasNehalem())
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if(MSR::IsAccessible() && MSR::HasPlatformInfo())
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{
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const u64 platformInfo = MSR::Read(MSR::NHM_PLATFORM_INFO);
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const u64 platformInfo = MSR::Read(MSR::PLATFORM_INFO);
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const u8 maxNonTurboRatio = bits(platformInfo, 8, 15);
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return maxNonTurboRatio * 133.33e6f;
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}
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