prefect
6fc1f45fa6
Added float-to-byte color conversion, including an SSE assembler version. Model renderer: Push UV coordinates into a shared vertex array and use bytes instead of floats for the color array, thereby, significantly reducing the total size of vertex arrays. This was SVN commit r2827.
111 lines
2.6 KiB
C
Executable File
111 lines
2.6 KiB
C
Executable File
// IA-32 (x86) specific code
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// Copyright (c) 2003 Jan Wassenberg
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//
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// This program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as
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// published by the Free Software Foundation; either version 2 of the
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// License, or (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but
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// WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// Contact info:
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// Jan.Wassenberg@stud.uni-karlsruhe.de
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// http://www.stud.uni-karlsruhe.de/~urkt/
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#ifndef IA32_H
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#define IA32_H
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#if !CPU_IA32
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#error "including ia32.h without CPU_IA32=1"
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#endif
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#include "lib/types.h"
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// some of these are implemented in asm, so make sure name mangling is
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// disabled.
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#ifdef __cplusplus
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extern "C" {
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#endif
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// call before any of the following functions
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extern void ia32_init();
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extern double _ceil(double);
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extern u64 rdtsc(void);
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#ifndef _MCW_PC
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#define _MCW_PC 0x0300 // Precision Control
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#endif
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#ifndef _PC_24
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#define _PC_24 0x0000 // 24 bits
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#endif
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#define _control87 ia32_control87
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extern uint ia32_control87(uint new_cw, uint mask); // asm
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extern void ia32_debug_break(void);
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extern void ia32_memcpy(void* dst, const void* src, size_t nbytes);
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// CPU caps (128 bits)
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// do not change the order!
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enum CpuCap
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{
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// standard (ecx) - currently only defined by Intel
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SSE3 = 0+0, // Streaming SIMD Extensions 3
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EST = 0+7, // Enhanced Speedstep Technology
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// standard (edx)
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TSC = 32+4, // TimeStamp Counter
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CMOV = 32+15, // Conditional MOVe
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MMX = 32+23, // MultiMedia eXtensions
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SSE = 32+25, // Streaming SIMD Extensions
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SSE2 = 32+26, // Streaming SIMD Extensions 2
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HT = 32+28, // HyperThreading
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// extended (ecx)
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// extended (edx) - currently only defined by AMD
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AMD_MP = 96+19, // MultiProcessing capable; reserved on AMD64
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AMD_3DNOW_PRO = 96+30,
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AMD_3DNOW = 96+31
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};
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extern bool ia32_cap(CpuCap cap);
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extern void ia32_get_cpu_info(void);
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extern void ia32_hook_capabilities(void);
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// internal use only
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// order in which registers are stored in regs array
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// (do not change! brand string relies on this ordering)
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enum IA32Regs
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{
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EAX,
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EBX,
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ECX,
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EDX
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};
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// try to call the specified CPUID sub-function. returns true on success or
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// false on failure (i.e. CPUID or the specific function not supported).
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// returns eax, ebx, ecx, edx registers in above order.
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extern bool ia32_cpuid(u32 func, u32* regs);
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#ifdef __cplusplus
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}
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#endif
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#endif // #ifndef IA32_H
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