2004-03-03 00:56:51 +01:00
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// IA-32 (x86) specific code
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// Copyright (c) 2003 Jan Wassenberg
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//
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// This program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as
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// published by the Free Software Foundation; either version 2 of the
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// License, or (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but
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// WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// Contact info:
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// Jan.Wassenberg@stud.uni-karlsruhe.de
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// http://www.stud.uni-karlsruhe.de/~urkt/
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2004-05-08 03:11:51 +02:00
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#include "precompiled.h"
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2004-03-03 00:56:51 +01:00
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#include "lib.h"
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2005-03-18 23:44:55 +01:00
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#include "posix.h"
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#include "ia32.h"
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2004-03-03 00:56:51 +01:00
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#include "detect.h"
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#include "timer.h"
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2004-06-03 20:46:21 +02:00
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// HACK (see call to wtime_reset_impl)
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2005-08-09 18:23:19 +02:00
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#if OS_WIN
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2004-06-03 20:46:21 +02:00
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#include "win/wtime.h"
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2004-03-03 00:56:51 +01:00
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#endif
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2005-06-28 06:06:25 +02:00
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2004-06-04 14:41:53 +02:00
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#include <string.h>
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#include <stdio.h>
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#include <vector>
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#include <algorithm>
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2005-08-09 18:23:19 +02:00
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#if HAVE_ASM
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2004-03-03 00:56:51 +01:00
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2005-08-09 18:23:19 +02:00
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// replace pathetic MS libc implementation.
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#if OS_WIN
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2004-03-03 00:56:51 +01:00
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double _ceil(double f)
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{
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double r;
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const float _49 = 0.499999f;
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2004-06-23 15:45:50 +02:00
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__asm
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{
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fld [f]
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fadd [_49]
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frndint
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fstp [r]
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}
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2004-03-03 00:56:51 +01:00
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2005-08-09 18:23:19 +02:00
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UNUSED2(f);
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2004-03-03 00:56:51 +01:00
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return r;
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}
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#endif
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// return convention for 64 bits with VC7.1, ICC8 is in edx:eax,
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// so temp variable is unnecessary, but we play it safe.
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inline u64 rdtsc()
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{
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u64 c;
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__asm
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{
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cpuid
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rdtsc
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2004-06-23 15:45:50 +02:00
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mov dword ptr [c], eax
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mov dword ptr [c+4], edx
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2004-03-03 00:56:51 +01:00
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}
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return c;
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}
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// change FPU control word (used to set precision)
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2005-01-31 00:07:55 +01:00
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uint ia32_control87(uint new_cw, uint mask)
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2004-03-03 00:56:51 +01:00
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{
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__asm
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{
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2004-06-23 15:45:50 +02:00
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push eax
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fnstcw [esp]
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pop eax ; old_cw
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mov ecx, [new_cw]
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mov edx, [mask]
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and ecx, edx ; new_cw & mask
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not edx ; ~mask
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and eax, edx ; old_cw & ~mask
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or eax, ecx ; (old_cw & ~mask) | (new_cw & mask)
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push eax
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fldcw [esp]
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pop eax
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2004-03-03 00:56:51 +01:00
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}
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2005-08-09 18:23:19 +02:00
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UNUSED2(new_cw);
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UNUSED2(mask);
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2004-03-03 00:56:51 +01:00
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return 0;
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}
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2004-07-12 18:40:57 +02:00
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void ia32_debug_break()
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{
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__asm int 3
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}
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2004-06-21 16:17:48 +02:00
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//
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// data returned by cpuid()
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// each function using this data must call cpuid (no-op if already called)
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//
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2004-03-03 00:56:51 +01:00
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2004-06-21 16:17:48 +02:00
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static char vendor_str[13];
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static int family, model, ext_family;
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// used in manual cpu_type detect
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2004-06-23 15:45:50 +02:00
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static u32 max_ext_func;
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2004-05-24 22:25:48 +02:00
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2004-06-21 16:17:48 +02:00
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// caps
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// treated as 128 bit field; order: std ecx, std edx, ext ecx, ext edx
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// keep in sync with enum CpuCap and cpuid() code!
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u32 caps[4];
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2004-03-03 00:56:51 +01:00
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2004-05-24 22:25:48 +02:00
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static int have_brand_string = 0;
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2004-06-21 16:17:48 +02:00
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// if false, need to detect cpu_type manually.
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2004-05-24 22:25:48 +02:00
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// int instead of bool for easier setting from asm
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2004-03-03 00:56:51 +01:00
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2004-10-03 15:06:37 +02:00
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// order in which registers are stored in regs array
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2004-06-23 15:45:50 +02:00
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enum Regs
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{
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EAX,
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EBX,
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ECX,
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EDX
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};
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2005-03-09 13:57:52 +01:00
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enum MiscCpuCapBits
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{
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// AMD PowerNow! flags (returned in edx by CPUID 0x80000007)
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POWERNOW_FREQ_ID_CTRL = 2
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};
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2004-06-23 15:45:50 +02:00
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static bool cpuid(u32 func, u32* regs)
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{
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if(func > max_ext_func)
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return false;
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2005-03-09 13:57:52 +01:00
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// (optimized for size)
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2004-06-23 15:45:50 +02:00
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__asm
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{
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mov eax, [func]
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cpuid
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mov edi, [regs]
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stosd
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xchg eax, ebx
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stosd
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xchg eax, ecx
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stosd
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xchg eax, edx
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stosd
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}
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return true;
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}
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2004-06-21 16:17:48 +02:00
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// (optimized for size)
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2005-07-16 19:49:38 +02:00
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static void cpuid()
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2004-03-03 00:56:51 +01:00
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{
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__asm
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{
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2005-07-20 02:54:39 +02:00
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pushad ;// save ebx, esi, edi, ebp
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;// ICC7: pusha is the 16-bit form!
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2004-03-03 00:56:51 +01:00
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2005-07-20 02:54:39 +02:00
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;// make sure CPUID is supported
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2004-03-03 00:56:51 +01:00
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pushfd
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or byte ptr [esp+2], 32
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popfd
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pushfd
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pop eax
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2005-07-20 02:54:39 +02:00
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shr eax, 22 ;// bit 21 toggled?
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2004-03-03 00:56:51 +01:00
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jnc no_cpuid
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2005-07-20 02:54:39 +02:00
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;// get vendor string
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2004-03-03 00:56:51 +01:00
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xor eax, eax
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cpuid
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2004-06-21 16:17:48 +02:00
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mov edi, offset vendor_str
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2004-03-03 00:56:51 +01:00
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xchg eax, ebx
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stosd
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xchg eax, edx
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stosd
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xchg eax, ecx
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stosd
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2005-07-20 02:54:39 +02:00
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;// (already 0 terminated)
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2004-03-03 00:56:51 +01:00
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2005-07-20 02:54:39 +02:00
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;// get CPU signature and std feature bits
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2004-03-03 00:56:51 +01:00
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push 1
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pop eax
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cpuid
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2004-06-21 16:17:48 +02:00
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mov [caps+0], ecx
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mov [caps+4], edx
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2004-06-19 16:46:44 +02:00
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movzx edx, al
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2004-03-03 00:56:51 +01:00
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shr edx, 4
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2005-07-20 02:54:39 +02:00
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mov [model], edx ;// eax[7:4]
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2004-06-19 16:46:44 +02:00
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movzx edx, ah
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2004-03-03 00:56:51 +01:00
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and edx, 0x0f
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2005-07-20 02:54:39 +02:00
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mov [family], edx ;// eax[11:8]
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2004-06-19 16:46:44 +02:00
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shr eax, 20
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2004-03-03 00:56:51 +01:00
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and eax, 0x0f
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2005-07-20 02:54:39 +02:00
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mov [ext_family], eax ;// eax[23:20]
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2004-03-03 00:56:51 +01:00
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2005-07-20 02:54:39 +02:00
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;// make sure CPUID ext functions are supported
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2004-03-03 00:56:51 +01:00
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mov esi, 0x80000000
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mov eax, esi
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cpuid
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2004-06-23 15:45:50 +02:00
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mov [max_ext_func], eax
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2005-07-20 02:54:39 +02:00
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cmp eax, esi ;// max ext <= 0x80000000?
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jbe no_ext_funcs ;// yes - no ext funcs at all
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lea esi, [esi+4] ;// esi = 0x80000004
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cmp eax, esi ;// max ext < 0x80000004?
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jb no_brand_str ;// yes - brand string not available, skip
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2004-03-03 00:56:51 +01:00
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2005-07-20 02:54:39 +02:00
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;// get CPU brand string (>= Athlon XP, P4)
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2004-03-03 00:56:51 +01:00
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mov edi, offset cpu_type
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push -2
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2005-07-20 02:54:39 +02:00
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pop esi ;// loop counter: [-2, 0]
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$1: lea eax, [0x80000004+esi] ;// 0x80000002 .. 4
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2004-03-03 00:56:51 +01:00
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cpuid
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stosd
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xchg eax, ebx
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stosd
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xchg eax, ecx
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stosd
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xchg eax, edx
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stosd
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2005-07-20 02:54:39 +02:00
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inc esi
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2004-03-03 00:56:51 +01:00
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jle $1
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2005-07-20 02:54:39 +02:00
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;// (already 0 terminated)
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2004-03-03 00:56:51 +01:00
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2005-07-20 02:54:39 +02:00
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mov [have_brand_string], esi ;// esi = 1 = true
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2004-05-24 22:25:48 +02:00
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2004-03-03 00:56:51 +01:00
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no_brand_str:
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2005-07-20 02:54:39 +02:00
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;// get extended feature flags
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mov eax, [0x80000001]
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2004-03-03 00:56:51 +01:00
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cpuid
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2004-06-21 16:17:48 +02:00
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mov [caps+8], ecx
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mov [caps+12], edx
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2004-03-03 00:56:51 +01:00
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no_ext_funcs:
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no_cpuid:
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popad
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2004-06-19 16:46:44 +02:00
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} // __asm
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} // cpuid()
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2004-03-03 00:56:51 +01:00
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2004-06-21 16:17:48 +02:00
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bool ia32_cap(CpuCap cap)
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{
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u32 idx = cap >> 5;
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if(idx > 3)
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{
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debug_warn("cap invalid");
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return false;
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}
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2005-07-16 19:49:38 +02:00
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u32 bit = BIT(cap & 0x1f);
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2004-06-21 16:17:48 +02:00
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return (caps[idx] & bit) != 0;
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}
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enum Vendor { UNKNOWN, INTEL, AMD };
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static Vendor vendor = UNKNOWN;
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2004-06-19 16:46:44 +02:00
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static void get_cpu_type()
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2004-03-03 00:56:51 +01:00
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{
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2005-03-01 21:13:00 +01:00
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// note: cpu_type is guaranteed to hold 48+1 chars, since that's the
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// length of the CPU brand string. strcpy(cpu_type, literal) is safe.
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2004-05-24 22:25:48 +02:00
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// fall back to manual detect of CPU type if it didn't supply
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// a brand string, or if the brand string is useless (i.e. "Unknown").
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if(!have_brand_string || strncmp(cpu_type, "Unknow", 6) == 0)
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// we use an extra flag to detect if we got the brand string:
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// safer than comparing against the default name, which may change.
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//
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// some older boards reprogram the brand string with
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// "Unknow[n] CPU Type" on CPUs the BIOS doesn't recognize.
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// in that case, we ignore the brand string and detect manually.
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{
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2004-06-21 16:17:48 +02:00
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if(vendor == AMD)
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2004-05-24 22:25:48 +02:00
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{
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// everything else is either too old, or should have a brand string.
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if(family == 6)
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{
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if(model == 3 || model == 7)
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2005-03-01 21:13:00 +01:00
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strcpy(cpu_type, "AMD Duron"); // safe
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2004-05-24 22:25:48 +02:00
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else if(model <= 5)
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2005-03-01 21:13:00 +01:00
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strcpy(cpu_type, "AMD Athlon"); // safe
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2004-05-24 22:25:48 +02:00
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else
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{
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2004-06-21 16:17:48 +02:00
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if(ia32_cap(MP))
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2005-03-01 21:13:00 +01:00
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strcpy(cpu_type, "AMD Athlon MP"); // safe
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2004-05-24 22:25:48 +02:00
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else
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2005-03-01 21:13:00 +01:00
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strcpy(cpu_type, "AMD Athlon XP"); // safe
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2004-05-24 22:25:48 +02:00
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}
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}
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}
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2004-06-21 16:17:48 +02:00
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else if(vendor == INTEL)
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2004-05-24 22:25:48 +02:00
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{
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// everything else is either too old, or should have a brand string.
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if(family == 6)
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{
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if(model == 1)
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2005-03-01 21:13:00 +01:00
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strcpy(cpu_type, "Intel Pentium Pro"); // safe
|
2004-05-24 22:25:48 +02:00
|
|
|
else if(model == 3 || model == 5)
|
2005-03-01 21:13:00 +01:00
|
|
|
strcpy(cpu_type, "Intel Pentium II"); // safe
|
2004-05-24 22:25:48 +02:00
|
|
|
else if(model == 6)
|
2005-03-01 21:13:00 +01:00
|
|
|
strcpy(cpu_type, "Intel Celeron"); // safe
|
2004-05-24 22:25:48 +02:00
|
|
|
else
|
2005-03-01 21:13:00 +01:00
|
|
|
strcpy(cpu_type, "Intel Pentium III"); // safe
|
2004-05-24 22:25:48 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// we have a valid brand string; try to pretty it up some
|
|
|
|
else
|
2004-03-03 00:56:51 +01:00
|
|
|
{
|
|
|
|
// strip (tm) from Athlon string
|
|
|
|
if(!strncmp(cpu_type, "AMD Athlon(tm)", 14))
|
|
|
|
memmove(cpu_type+10, cpu_type+14, 34);
|
|
|
|
|
|
|
|
// remove 2x (R) and CPU freq from P4 string
|
2004-06-13 18:04:11 +02:00
|
|
|
float freq;
|
2004-06-19 16:46:44 +02:00
|
|
|
// the indicated frequency isn't necessarily correct - the CPU may be
|
|
|
|
// overclocked. need to pass a variable though, since scanf returns
|
|
|
|
// the number of fields actually stored.
|
2004-06-13 18:04:11 +02:00
|
|
|
if(sscanf(cpu_type, " Intel(R) Pentium(R) 4 CPU %fGHz", &freq) == 1)
|
2005-03-01 21:13:00 +01:00
|
|
|
strcpy(cpu_type, "Intel Pentium 4"); // safe
|
2004-03-03 00:56:51 +01:00
|
|
|
}
|
2004-06-19 16:46:44 +02:00
|
|
|
}
|
2004-05-24 22:25:48 +02:00
|
|
|
|
|
|
|
|
2004-06-19 16:46:44 +02:00
|
|
|
static void measure_cpu_freq()
|
|
|
|
{
|
2004-10-03 15:06:37 +02:00
|
|
|
// set max priority, to reduce interference while measuring.
|
|
|
|
int old_policy; static sched_param old_param; // (static => 0-init)
|
2004-03-03 00:56:51 +01:00
|
|
|
pthread_getschedparam(pthread_self(), &old_policy, &old_param);
|
|
|
|
static sched_param max_param;
|
2004-12-07 04:01:12 +01:00
|
|
|
max_param.sched_priority = sched_get_priority_max(SCHED_FIFO);
|
|
|
|
pthread_setschedparam(pthread_self(), SCHED_FIFO, &max_param);
|
2004-03-03 00:56:51 +01:00
|
|
|
|
2004-06-23 15:45:50 +02:00
|
|
|
if(ia32_cap(TSC))
|
2004-10-03 15:06:37 +02:00
|
|
|
// make sure the TSC is available, because we're going to
|
|
|
|
// measure actual CPU clocks per known time interval.
|
2004-06-23 15:45:50 +02:00
|
|
|
// counting loop iterations ("bogomips") is unreliable.
|
2004-03-03 00:56:51 +01:00
|
|
|
{
|
2004-10-03 15:06:37 +02:00
|
|
|
// note: no need to "warm up" cpuid - it will already have been
|
|
|
|
// called several times by the time this code is reached.
|
|
|
|
// (background: it's used in rdtsc() to serialize instruction flow;
|
|
|
|
// the first call is documented to be slower on Intel CPUs)
|
2004-03-03 00:56:51 +01:00
|
|
|
|
2004-06-19 16:46:44 +02:00
|
|
|
int num_samples = 16;
|
2004-06-23 15:45:50 +02:00
|
|
|
// if clock is low-res, do less samples so it doesn't take too long.
|
|
|
|
// balance measuring time (~ 10 ms) and accuracy (< 1 0/00 error -
|
|
|
|
// ok for using the TSC as a time reference)
|
2004-03-03 00:56:51 +01:00
|
|
|
if(timer_res() >= 1e-3)
|
2004-06-19 16:46:44 +02:00
|
|
|
num_samples = 8;
|
2004-06-23 15:45:50 +02:00
|
|
|
std::vector<double> samples(num_samples);
|
2004-03-03 00:56:51 +01:00
|
|
|
|
|
|
|
int i;
|
|
|
|
for(i = 0; i < num_samples; i++)
|
|
|
|
{
|
2004-06-23 15:45:50 +02:00
|
|
|
double dt;
|
|
|
|
i64 dc;
|
|
|
|
// i64 because VC6 can't convert u64 -> double,
|
|
|
|
// and we don't need all 64 bits.
|
|
|
|
|
2004-10-03 15:06:37 +02:00
|
|
|
// count # of clocks in max{1 tick, 1 ms}:
|
|
|
|
// .. wait for start of tick.
|
2004-06-23 15:45:50 +02:00
|
|
|
const double t0 = get_time();
|
|
|
|
u64 c1; double t1;
|
2004-03-03 00:56:51 +01:00
|
|
|
do
|
|
|
|
{
|
2004-10-03 15:06:37 +02:00
|
|
|
// note: get_time effectively has a long delay (up to 5 �s)
|
|
|
|
// before returning the time. we call it before rdtsc to
|
|
|
|
// minimize the delay between actually sampling time / TSC,
|
|
|
|
// thus decreasing the chance for interference.
|
|
|
|
// (if unavoidable background activity, e.g. interrupts,
|
|
|
|
// delays the second reading, inaccuracy is introduced).
|
2004-06-23 15:45:50 +02:00
|
|
|
t1 = get_time();
|
2004-10-03 15:06:37 +02:00
|
|
|
c1 = rdtsc();
|
2004-03-03 00:56:51 +01:00
|
|
|
}
|
2004-06-23 15:45:50 +02:00
|
|
|
while(t1 == t0);
|
2004-10-03 15:06:37 +02:00
|
|
|
// .. wait until start of next tick and at least 1 ms elapsed.
|
2004-03-03 00:56:51 +01:00
|
|
|
do
|
|
|
|
{
|
2004-06-23 15:45:50 +02:00
|
|
|
const double t2 = get_time();
|
2004-10-03 15:06:37 +02:00
|
|
|
const u64 c2 = rdtsc();
|
2004-06-23 15:45:50 +02:00
|
|
|
dc = (i64)(c2 - c1);
|
|
|
|
dt = t2 - t1;
|
2004-03-03 00:56:51 +01:00
|
|
|
}
|
2004-06-23 15:45:50 +02:00
|
|
|
while(dt < 1e-3);
|
2004-03-03 00:56:51 +01:00
|
|
|
|
|
|
|
// .. freq = (delta_clocks) / (delta_seconds);
|
2004-10-03 15:06:37 +02:00
|
|
|
// cpuid/rdtsc/timer overhead is negligible.
|
2004-06-23 15:45:50 +02:00
|
|
|
const double freq = dc / dt;
|
|
|
|
samples[i] = freq;
|
2004-03-03 00:56:51 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
std::sort(samples.begin(), samples.end());
|
|
|
|
|
2004-10-03 15:06:37 +02:00
|
|
|
// median filter (remove upper and lower 25% and average the rest).
|
|
|
|
// note: don't just take the lowest value! it could conceivably be
|
|
|
|
// too low, if background processing delays reading c1 (see above).
|
2004-03-03 00:56:51 +01:00
|
|
|
double sum = 0.0;
|
|
|
|
const int lo = num_samples/4, hi = 3*num_samples/4;
|
|
|
|
for(i = lo; i < hi; i++)
|
|
|
|
sum += samples[i];
|
|
|
|
cpu_freq = sum / (hi-lo);
|
2004-10-03 15:06:37 +02:00
|
|
|
|
2004-03-03 00:56:51 +01:00
|
|
|
}
|
2004-10-03 15:06:37 +02:00
|
|
|
// else: TSC not available, can't measure; cpu_freq remains unchanged.
|
2004-03-03 00:56:51 +01:00
|
|
|
|
2004-10-03 15:06:37 +02:00
|
|
|
// restore previous policy and priority.
|
2004-03-03 00:56:51 +01:00
|
|
|
pthread_setschedparam(pthread_self(), old_policy, &old_param);
|
|
|
|
}
|
|
|
|
|
2004-06-19 16:46:44 +02:00
|
|
|
|
|
|
|
int get_cur_processor_id()
|
|
|
|
{
|
|
|
|
int apic_id;
|
|
|
|
__asm {
|
|
|
|
push 1
|
|
|
|
pop eax
|
|
|
|
cpuid
|
|
|
|
shr ebx, 24
|
|
|
|
mov [apic_id], ebx ; ebx[31:24]
|
|
|
|
}
|
|
|
|
|
|
|
|
return apic_id;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2004-06-22 19:20:38 +02:00
|
|
|
// set cpu_smp if there's more than 1 physical CPU -
|
|
|
|
// need to know this for wtime's TSC safety check.
|
2004-09-02 04:47:11 +02:00
|
|
|
// called on each CPU by on_each_cpu.
|
2004-06-23 15:45:50 +02:00
|
|
|
static void check_smp()
|
2004-06-19 16:46:44 +02:00
|
|
|
{
|
2005-06-28 06:06:25 +02:00
|
|
|
debug_assert(cpus > 0 && "must know # CPUs (call OS-specific detect first)");
|
2004-06-19 16:46:44 +02:00
|
|
|
|
|
|
|
// we don't check if it's Intel and P4 or above - HT may be supported
|
|
|
|
// on other CPUs in future. haven't come across a processor that
|
|
|
|
// incorrectly sets the HT feature bit.
|
2004-06-21 16:17:48 +02:00
|
|
|
if(!ia32_cap(HT))
|
2004-06-22 19:20:38 +02:00
|
|
|
{
|
|
|
|
// no HT supported, just check number of CPUs as reported by OS.
|
|
|
|
cpu_smp = (cpus > 1);
|
2004-06-19 16:46:44 +02:00
|
|
|
return;
|
2004-06-22 19:20:38 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
// first call. we set cpu_smp below if more than 1 physical CPU is found,
|
|
|
|
// so clear it until then.
|
|
|
|
if(cpu_smp == -1)
|
|
|
|
cpu_smp = 0;
|
|
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
// still need to check if HT is actually enabled (BIOS and OS);
|
|
|
|
// there might be 2 CPUs with HT supported but disabled.
|
|
|
|
//
|
2004-06-19 16:46:44 +02:00
|
|
|
|
|
|
|
// get number of logical CPUs per package
|
2004-06-22 19:20:38 +02:00
|
|
|
// (the same for all packages on this system)
|
2004-06-19 16:46:44 +02:00
|
|
|
int log_cpus_per_package;
|
|
|
|
__asm {
|
|
|
|
push 1
|
|
|
|
pop eax
|
|
|
|
cpuid
|
|
|
|
shr ebx, 16
|
|
|
|
and ebx, 0xff
|
|
|
|
mov log_cpus_per_package, ebx ; ebx[23:16]
|
|
|
|
}
|
|
|
|
|
2004-06-22 19:20:38 +02:00
|
|
|
// logical CPUs are initialized after one another =>
|
|
|
|
// they have the same physical ID.
|
|
|
|
const int id = get_cur_processor_id();
|
|
|
|
const int phys_shift = log2(log_cpus_per_package);
|
|
|
|
const int phys_id = id >> phys_shift;
|
|
|
|
|
|
|
|
// more than 1 physical CPU found
|
|
|
|
static int last_phys_id = -1;
|
2004-06-23 15:45:50 +02:00
|
|
|
if(last_phys_id != -1 && last_phys_id != phys_id)
|
2004-06-22 19:20:38 +02:00
|
|
|
cpu_smp = 1;
|
2004-06-23 15:45:50 +02:00
|
|
|
last_phys_id = phys_id;
|
2004-06-19 16:46:44 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2004-06-21 16:17:48 +02:00
|
|
|
static void check_speedstep()
|
|
|
|
{
|
2005-03-09 13:57:52 +01:00
|
|
|
if(vendor == INTEL)
|
|
|
|
{
|
|
|
|
if(ia32_cap(EST))
|
|
|
|
cpu_speedstep = 1;
|
|
|
|
}
|
|
|
|
else if(vendor == AMD)
|
2004-06-23 15:45:50 +02:00
|
|
|
{
|
|
|
|
u32 regs[4];
|
|
|
|
if(cpuid(0x80000007, regs))
|
2005-03-09 13:57:52 +01:00
|
|
|
if(regs[EDX] & POWERNOW_FREQ_ID_CTRL)
|
2004-06-23 15:45:50 +02:00
|
|
|
cpu_speedstep = 1;
|
|
|
|
}
|
2004-06-21 16:17:48 +02:00
|
|
|
}
|
|
|
|
|
2004-06-21 18:29:47 +02:00
|
|
|
|
2004-06-19 16:46:44 +02:00
|
|
|
void ia32_get_cpu_info()
|
|
|
|
{
|
|
|
|
cpuid();
|
2004-06-21 16:17:48 +02:00
|
|
|
if(family == 0) // cpuid not supported - can't do the rest
|
2004-06-19 16:46:44 +02:00
|
|
|
return;
|
|
|
|
|
|
|
|
// (for easier comparison)
|
2004-06-21 16:17:48 +02:00
|
|
|
if(!strcmp(vendor_str, "AuthenticAMD"))
|
|
|
|
vendor = AMD;
|
|
|
|
else if(!strcmp(vendor_str, "GenuineIntel"))
|
|
|
|
vendor = INTEL;
|
2004-06-19 16:46:44 +02:00
|
|
|
|
|
|
|
get_cpu_type();
|
2004-06-21 18:29:47 +02:00
|
|
|
check_speedstep();
|
2004-06-23 15:45:50 +02:00
|
|
|
on_each_cpu(check_smp);
|
2004-06-27 03:42:55 +02:00
|
|
|
|
|
|
|
measure_cpu_freq();
|
|
|
|
|
2005-08-09 18:23:19 +02:00
|
|
|
// HACK: on Windows, the HRT makes its final implementation choice
|
2004-06-27 03:42:55 +02:00
|
|
|
// in the first calibrate call where cpu info is available.
|
|
|
|
// call wtime_reset_impl here to have that happen now,
|
|
|
|
// so app code isn't surprised by a timer change, although the HRT
|
|
|
|
// does try to keep the timer continuous.
|
2005-08-09 18:23:19 +02:00
|
|
|
#if OS_WIN
|
2004-06-27 03:42:55 +02:00
|
|
|
wtime_reset_impl();
|
|
|
|
#endif
|
2004-06-19 16:46:44 +02:00
|
|
|
}
|
|
|
|
|
2005-05-03 07:05:16 +02:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2005-07-04 19:03:08 +02:00
|
|
|
// CAS does a sanity check on the location parameter to see if the caller
|
|
|
|
// actually is passing an address (instead of a value, e.g. 1). this is
|
|
|
|
// important because the call is via a macro that coerces parameters.
|
|
|
|
//
|
|
|
|
// reporting is done with the regular CRT assert instead of debug_assert
|
|
|
|
// because the wdbg code relies on CAS internally (e.g. to avoid
|
|
|
|
// nested stack traces). a bug such as VC's incorrect handling of params
|
|
|
|
// in __declspec(naked) functions would then cause infinite recursion,
|
|
|
|
// which is difficult to debug (since wdbg is hosed) and quite fatal.
|
|
|
|
#define ASSERT(x) assert(x)
|
2005-05-03 07:05:16 +02:00
|
|
|
|
|
|
|
// note: a 486 or later processor is required since we use CMPXCHG.
|
|
|
|
// there's no feature flag we can check, and the ia32 code doesn't
|
|
|
|
// bother detecting anything < Pentium, so this'll crash and burn if
|
|
|
|
// run on 386. we could replace cmpxchg with a simple mov (since 386
|
|
|
|
// CPUs aren't MP-capable), but it's not worth the trouble.
|
|
|
|
|
2005-07-04 04:43:54 +02:00
|
|
|
// note: don't use __declspec(naked) because we need to access one parameter
|
|
|
|
// from C code and VC can't handle that correctly.
|
|
|
|
bool __cdecl CAS_(uintptr_t* location, uintptr_t expected, uintptr_t new_value)
|
2005-05-03 07:05:16 +02:00
|
|
|
{
|
|
|
|
// try to see if caller isn't passing in an address
|
|
|
|
// (CAS's arguments are silently casted)
|
2005-08-09 18:23:19 +02:00
|
|
|
ASSERT(!debug_is_pointer_bogus(location));
|
2005-05-03 07:05:16 +02:00
|
|
|
|
2005-07-04 04:43:54 +02:00
|
|
|
bool was_updated;
|
2005-05-03 07:05:16 +02:00
|
|
|
__asm
|
|
|
|
{
|
|
|
|
cmp byte ptr [cpus], 1
|
2005-07-04 04:43:54 +02:00
|
|
|
mov eax, [expected]
|
|
|
|
mov edx, [location]
|
|
|
|
mov ecx, [new_value]
|
2005-05-03 07:05:16 +02:00
|
|
|
je $no_lock
|
|
|
|
_emit 0xf0 // LOCK prefix
|
|
|
|
$no_lock:
|
|
|
|
cmpxchg [edx], ecx
|
|
|
|
sete al
|
2005-07-04 04:43:54 +02:00
|
|
|
mov [was_updated], al
|
2005-05-03 07:05:16 +02:00
|
|
|
}
|
2005-07-04 04:43:54 +02:00
|
|
|
return was_updated;
|
2005-05-03 07:05:16 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-07-16 19:49:38 +02:00
|
|
|
void atomic_add(intptr_t* location, intptr_t increment)
|
2005-05-03 07:05:16 +02:00
|
|
|
{
|
|
|
|
__asm
|
|
|
|
{
|
|
|
|
cmp byte ptr [cpus], 1
|
2005-07-16 19:49:38 +02:00
|
|
|
mov edx, [location]
|
|
|
|
mov eax, [increment]
|
2005-05-03 07:05:16 +02:00
|
|
|
je $no_lock
|
|
|
|
_emit 0xf0 // LOCK prefix
|
|
|
|
$no_lock:
|
|
|
|
add [edx], eax
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// enforce strong memory ordering.
|
|
|
|
void mfence()
|
|
|
|
{
|
|
|
|
// Pentium IV
|
|
|
|
if(ia32_cap(SSE2))
|
|
|
|
__asm mfence
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void serialize()
|
|
|
|
{
|
|
|
|
__asm cpuid
|
|
|
|
}
|
|
|
|
|
2005-08-09 18:23:19 +02:00
|
|
|
#else // i.e. #if !HAVE_ASM
|
2005-05-18 07:32:09 +02:00
|
|
|
|
|
|
|
bool CAS_(uintptr_t* location, uintptr_t expected, uintptr_t new_value)
|
|
|
|
{
|
|
|
|
uintptr_t prev;
|
2005-07-04 04:43:54 +02:00
|
|
|
|
2005-08-07 23:58:36 +02:00
|
|
|
debug_assert(location >= (uintptr_t*)0x10000);
|
2005-07-04 04:43:54 +02:00
|
|
|
|
2005-05-18 07:32:09 +02:00
|
|
|
__asm__ __volatile__("lock; cmpxchgl %1,%2"
|
|
|
|
: "=a"(prev) // %0: Result in eax should be stored in prev
|
|
|
|
: "q"(new_value), // %1: new_value -> e[abcd]x
|
|
|
|
"m"(*location), // %2: Memory operand
|
|
|
|
"0"(expected) // Stored in same place as %0
|
|
|
|
: "memory"); // We make changes in memory
|
2005-07-04 04:43:54 +02:00
|
|
|
return prev == expected;
|
2005-05-18 07:32:09 +02:00
|
|
|
}
|
|
|
|
|
2005-07-04 04:43:54 +02:00
|
|
|
void atomic_add(intptr_t* location, intptr_t increment)
|
2005-05-18 07:32:09 +02:00
|
|
|
{
|
|
|
|
__asm__ __volatile__ (
|
|
|
|
"cmpb $1, %1;"
|
|
|
|
"je 1f;"
|
|
|
|
"lock;"
|
|
|
|
"1: addl %3, %0"
|
|
|
|
: "=m" (*location) /* %0: Output into *location */
|
|
|
|
: "m" (cpus), /* %1: Input for cpu check */
|
|
|
|
"m" (*location), /* %2: *location is also an input */
|
|
|
|
"r" (increment) /* %3: Increment (store in register) */
|
|
|
|
: "memory"); /* clobbers memory (*location) */
|
|
|
|
}
|
|
|
|
|
|
|
|
void mfence()
|
|
|
|
{
|
|
|
|
// no cpu caps stored in gcc compiles, so we can't check for SSE2 support
|
|
|
|
/*
|
|
|
|
if (ia32_cap(SSE2))
|
|
|
|
__asm__ __volatile__ ("mfence");
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
|
|
|
|
void serialize()
|
|
|
|
{
|
|
|
|
__asm__ __volatile__ ("cpuid");
|
|
|
|
}
|
|
|
|
|
2005-08-09 18:23:19 +02:00
|
|
|
#endif // #if HAVE_ASM
|