further refactoring of new cache detect code
- add invariant - level/type are always valid, numEntries indicates whether the cache is actually present and not disabled - handle pseudo-descriptors 0xF0 and F1 (avoids warning) This was SVN commit r9083.
This commit is contained in:
parent
4ae8cfe858
commit
fb499ff0d0
@ -37,7 +37,7 @@ static x86_x64_Cache caches[numCaches];
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static void AddCache(const x86_x64_Cache& cache)
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{
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debug_assert(1 <= cache.level && cache.level <= x86_x64_Cache::maxLevels);
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debug_assert(cache.Validate());
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if(cache.type == x86_x64_Cache::kData || cache.type == x86_x64_Cache::kUnified)
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caches[L1D + cache.level-1] = cache;
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@ -48,6 +48,7 @@ static void AddCache(const x86_x64_Cache& cache)
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static void AddTLB(const x86_x64_Cache& tlb)
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{
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debug_assert(tlb.Validate());
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debug_assert(tlb.level == 1 || tlb.level == 2); // see maxTLBs
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debug_assert(numTLBs < maxTLBs);
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@ -66,19 +67,23 @@ namespace AMD
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static x86_x64_Cache L1Cache(u32 reg, x86_x64_Cache::Type type)
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{
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x86_x64_Cache cache;
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memset(&cache, 0, sizeof(cache));
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cache.type = type;
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cache.level = 1;
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cache.associativity = bits(reg, 16, 23);
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cache.entrySize = bits(reg, 0, 7);
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cache.sharedBy = 1;
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if (cache.entrySize)
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cache.numEntries = bits(reg, 24, 31)*KiB / cache.entrySize;
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cache.Initialize(1, type);
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const size_t lineSize = bits(reg, 0, 7);
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const size_t associativity = bits(reg, 16, 23); // 0 = reserved
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const size_t totalSize = bits(reg, 24, 31)*KiB;
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if(lineSize != 0 && associativity != 0 && totalSize != 0)
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{
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cache.numEntries = totalSize / lineSize;
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cache.entrySize = lineSize;
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cache.associativity = associativity;
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cache.sharedBy = 1;
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}
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return cache;
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}
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// applies to L2, L3 and TLB2
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static const size_t associativities[16] =
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static const size_t associativityTable[16] =
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{
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0, 1, 2, 0, 4, 0, 8, 0,
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16, 0, 32, 48, 64, 96, 128, x86_x64_Cache::fullyAssociative
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@ -87,69 +92,72 @@ static const size_t associativities[16] =
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static x86_x64_Cache L2Cache(u32 reg, x86_x64_Cache::Type type)
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{
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x86_x64_Cache cache;
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memset(&cache, 0, sizeof(cache));
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const size_t associativityIndex = bits(reg, 12, 15);
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if(associativityIndex == 0) // disabled
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cache.Initialize(2, type);
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const size_t lineSize = bits(reg, 0, 7);
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const size_t idxAssociativity = bits(reg, 12, 15); // 0 = disabled
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const size_t totalSize = bits(reg, 16, 31)*KiB;
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if(lineSize != 0 && idxAssociativity != 0 && totalSize != 0)
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{
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cache.type = x86_x64_Cache::kNull;
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cache.associativity = 0;
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cache.numEntries = totalSize / lineSize;
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cache.entrySize = lineSize;
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cache.associativity = associativityTable[idxAssociativity];
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cache.sharedBy = 1;
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}
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else
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{
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cache.type = type;
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cache.associativity = associativities[associativityIndex];
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debug_assert(cache.associativity != 0); // else: encoding is "reserved"
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}
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cache.level = 2;
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cache.entrySize = bits(reg, 0, 7);
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cache.sharedBy = 1;
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if (cache.entrySize)
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cache.numEntries = bits(reg, 16, 31)*KiB / cache.entrySize;
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return cache;
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}
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// (same as L2 except for the size)
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static x86_x64_Cache L3Cache(u32 reg, x86_x64_Cache::Type type)
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{
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x86_x64_Cache cache = L2Cache(reg, type);
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cache.level = 3;
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if (cache.entrySize)
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cache.numEntries = bits(reg, 18, 31)*512*KiB / cache.entrySize; // (rounded down)
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x86_x64_Cache cache;
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cache.Initialize(3, type);
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const size_t lineSize = bits(reg, 0, 7);
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const size_t idxAssociativity = bits(reg, 12, 15); // 0 = disabled
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const size_t totalSize = bits(reg, 18, 31)*512*KiB; // (rounded down)
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// NB: some Athlon 64 X2 models have no L3 cache
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if(lineSize != 0 && idxAssociativity != 0 && totalSize != 0)
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{
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cache.numEntries = totalSize / lineSize;
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cache.entrySize = lineSize;
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cache.associativity = associativityTable[idxAssociativity];
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cache.sharedBy = 1;
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}
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return cache;
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}
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static x86_x64_Cache TLB1(u32 reg, size_t bitOffset, size_t pageSize, x86_x64_Cache::Type type)
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{
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x86_x64_Cache cache;
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memset(&cache, 0, sizeof(cache));
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cache.type = type;
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cache.level = 1;
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cache.associativity = bits(reg, bitOffset+8, bitOffset+15);
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cache.entrySize = pageSize;
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cache.sharedBy = 1;
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cache.numEntries = bits(reg, bitOffset, bitOffset+7);
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cache.Initialize(1, type);
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const size_t numEntries = bits(reg, bitOffset+0, bitOffset+ 7);
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const size_t associativity = bits(reg, bitOffset+8, bitOffset+15); // 0 = reserved
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if(numEntries != 0 && associativity != 0)
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{
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cache.numEntries = numEntries;
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cache.entrySize = pageSize;
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cache.associativity = associativity;
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cache.sharedBy = 1;
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}
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return cache;
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}
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static x86_x64_Cache TLB2(u32 reg, size_t bitOffset, size_t pageSize, x86_x64_Cache::Type type)
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{
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x86_x64_Cache cache;
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memset(&cache, 0, sizeof(cache));
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const size_t associativityIndex = bits(reg, bitOffset+12, bitOffset+15);
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if(associativityIndex == 0) // disabled
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cache.Initialize(2, type);
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const size_t numEntries = bits(reg, bitOffset+ 0, bitOffset+11);
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const size_t idxAssociativity = bits(reg, bitOffset+12, bitOffset+15); // 0 = disabled
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if(numEntries != 0 && idxAssociativity != 0)
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{
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cache.type = x86_x64_Cache::kNull;
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cache.associativity = 0;
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cache.numEntries = numEntries;
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cache.entrySize = pageSize;
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cache.associativity = associativityTable[idxAssociativity];
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cache.sharedBy = 1;
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}
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else
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{
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cache.type = type;
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cache.associativity = associativities[associativityIndex];
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}
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cache.level = 2;
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cache.entrySize = pageSize;
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cache.sharedBy = 1;
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cache.numEntries = bits(reg, bitOffset, bitOffset+11);
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return cache;
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}
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@ -187,7 +195,6 @@ static void DetectCacheAndTLB()
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{
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AddCache(L2Cache(regs.ecx, x86_x64_Cache::kUnified));
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AddCache(L3Cache(regs.edx, x86_x64_Cache::kUnified));
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// NB: some Athlon 64 X2 models report L3 type == null
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AddTLB2Pair(regs.eax, 2*MiB);
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AddTLB2Pair(regs.ebx, 4*KiB);
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@ -213,22 +220,21 @@ static bool DetectCache()
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if(!x86_x64_cpuid(®s))
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return false;
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const x86_x64_Cache::Type type = (x86_x64_Cache::Type)bits(regs.eax, 0, 4);
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const x86_x64_Cache::Type type = (x86_x64_Cache::Type)bits(regs.eax, 0, 4);
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if(type == x86_x64_Cache::kNull) // no more remaining
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break;
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const size_t level = (size_t)bits(regs.eax, 5, 7);
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const size_t partitions = (size_t)bits(regs.ebx, 12, 21)+1;
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const size_t sets = (size_t)bits(regs.ecx, 0, 31)+1;
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if(type == x86_x64_Cache::kNull) // no more remaining
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break;
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x86_x64_Cache cache;
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memset(&cache, 0, sizeof(cache));
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cache.type = type;
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cache.level = level;
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cache.associativity = (size_t)bits(regs.ebx, 22, 31)+1;
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cache.entrySize = (size_t)bits(regs.ebx, 0, 11)+1; // (yes, this also uses +1 encoding)
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cache.sharedBy = (size_t)bits(regs.eax, 14, 25)+1;
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cache.Initialize(level, type);
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cache.numEntries = cache.associativity * partitions * sets;
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cache.entrySize = (size_t)bits(regs.ebx, 0, 11)+1; // (yes, this also uses +1 encoding)
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cache.associativity = (size_t)bits(regs.ebx, 22, 31)+1;
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cache.sharedBy = (size_t)bits(regs.eax, 14, 25)+1;
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AddCache(cache);
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}
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@ -342,16 +348,16 @@ struct Characteristics // POD
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return smallSize >= 0;
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}
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size_t EntrySize() const
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{
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return IsTLB()? (flags & ~0xF) : -smallSize;
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}
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size_t NumEntries() const
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{
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return IsTLB()? smallSize : (flags & ~0xF);
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}
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size_t EntrySize() const
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{
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return IsTLB()? (flags & ~0xF) : -smallSize;
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}
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u8 descriptor;
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u8 associativity;
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i16 smallSize; // negative cache entrySize or TLB numEntries
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@ -526,26 +532,49 @@ static const Characteristics* CharacteristicsFromDescriptor(Descriptor descripto
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enum DescriptorFlags
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{
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SKIP_CACHE_DESCRIPTORS = 1,
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NO_LAST_LEVEL_CACHE = 2
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NO_LAST_LEVEL_CACHE = 2,
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PREFETCH64 = 64,
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PREFETCH128 = 128,
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};
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static bool HandleSpecialDescriptor(Descriptor descriptor, size_t& descriptorFlags)
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{
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switch(descriptor)
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{
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case 0: // carries no information
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return true;
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case 0x40:
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descriptorFlags |= NO_LAST_LEVEL_CACHE;
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return true;
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case 0xF0:
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descriptorFlags |= PREFETCH64;
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return true;
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case 0xF1:
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descriptorFlags |= PREFETCH128;
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return true;
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case 0xFF: // descriptors don't include caches (use CPUID.4 instead)
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descriptorFlags |= SKIP_CACHE_DESCRIPTORS;
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return true;
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default:
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return false;
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}
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}
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static void DetectCacheAndTLB(size_t& descriptorFlags)
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{
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const Descriptors descriptors = GetDescriptors();
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for(Descriptors::const_iterator it = descriptors.begin(); it != descriptors.end(); ++it)
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{
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const Descriptor descriptor = *it;
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switch(descriptor)
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{
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case 0: // carries no information
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if(HandleSpecialDescriptor(descriptor, descriptorFlags))
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continue;
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case 0x40:
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descriptorFlags |= NO_LAST_LEVEL_CACHE;
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continue;
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case 0xFF: // descriptors don't include caches (use CPUID.4 instead)
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descriptorFlags |= SKIP_CACHE_DESCRIPTORS;
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continue;
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}
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const Characteristics* characteristics = CharacteristicsFromDescriptor(*it);
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if(!characteristics)
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continue;
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@ -554,13 +583,11 @@ static void DetectCacheAndTLB(size_t& descriptorFlags)
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continue;
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x86_x64_Cache cache;
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memset(&cache, 0, sizeof(cache));
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cache.type = characteristics->Type();
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cache.level = characteristics->Level();
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cache.associativity = characteristics->associativity;
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cache.entrySize = characteristics->EntrySize();
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cache.sharedBy = 1; // (safe default)
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cache.Initialize(characteristics->Level(), characteristics->Type());
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cache.numEntries = characteristics->NumEntries();
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cache.entrySize = characteristics->EntrySize();
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cache.associativity = characteristics->associativity;
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cache.sharedBy = 1; // (safe default)
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if(characteristics->IsTLB())
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AddTLB(cache);
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else
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@ -573,8 +600,12 @@ static void DetectCacheAndTLB(size_t& descriptorFlags)
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static LibError DetectCacheAndTLB()
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{
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for(size_t i = 0; i < ARRAY_SIZE(caches); i++)
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caches[i].Init();
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// ensure all cache entries are initialized (DetectCache* might not set them all)
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for(size_t idxLevel = 0; idxLevel < x86_x64_Cache::maxLevels; idxLevel++)
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{
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caches[L1D+idxLevel].Initialize(idxLevel+1, x86_x64_Cache::kData);
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caches[L1I+idxLevel].Initialize(idxLevel+1, x86_x64_Cache::kInstruction);
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}
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if(x86_x64_Vendor() == X86_X64_VENDOR_AMD)
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AMD::DetectCacheAndTLB();
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@ -587,18 +618,18 @@ static LibError DetectCacheAndTLB()
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}
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// sanity checks
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for(size_t i = 0; i < x86_x64_Cache::maxLevels; i++)
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for(size_t idxLevel = 0; idxLevel < x86_x64_Cache::maxLevels; idxLevel++)
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{
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debug_assert(caches[L1D+i].type != x86_x64_Cache::kInstruction);
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if(caches[L1D+i].type != x86_x64_Cache::kNull)
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debug_assert(caches[L1D+i].level == i+1);
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debug_assert(caches[L1D+i].Validate() == true);
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debug_assert(caches[L1D+idxLevel].type == x86_x64_Cache::kData || caches[L1D+idxLevel].type == x86_x64_Cache::kUnified);
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debug_assert(caches[L1D+idxLevel].level == idxLevel+1);
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debug_assert(caches[L1D+idxLevel].Validate() == true);
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debug_assert(caches[L1I+i].type != x86_x64_Cache::kData);
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if(caches[L1I+i].type != x86_x64_Cache::kNull)
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debug_assert(caches[L1I+i].level == i+1);
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debug_assert(caches[L1I+i].Validate() == true);
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debug_assert(caches[L1I+idxLevel].type == x86_x64_Cache::kInstruction || caches[L1I+idxLevel].type == x86_x64_Cache::kUnified);
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debug_assert(caches[L1I+idxLevel].level == idxLevel+1);
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debug_assert(caches[L1I+idxLevel].Validate() == true);
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}
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for(size_t i = 0; i < numTLBs; i++)
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debug_assert(caches[TLB+i].Validate() == true);
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return INFO::OK;
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}
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@ -37,29 +37,77 @@ struct x86_x64_Cache // POD (may be used before static constructors)
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static const size_t maxLevels = 3;
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static const size_t fullyAssociative = 0xFF;
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static const size_t fullyAssociative = 0xFF; // (CPUID.4 definition)
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void Init()
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/**
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* 1..maxLevels
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**/
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size_t level;
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/**
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* never kNull
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**/
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Type type;
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/**
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* if 0, the cache is disabled and all other values are zero
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**/
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size_t numEntries;
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/**
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* NB: cache entries are lines, TLB entries are pages
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**/
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size_t entrySize;
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/**
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* = fullyAssociative or the actual ways of associativity
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**/
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size_t associativity;
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/**
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* how many logical processors share this cache?
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**/
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size_t sharedBy;
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void Initialize(size_t level, Type type)
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{
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type = kNull;
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level = 0;
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this->level = level;
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this->type = type;
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numEntries = 0;
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entrySize = 0;
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associativity = 0;
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entrySize = 0;
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sharedBy = 0;
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numEntries = 0;
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sharedBy = 0;
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debug_assert(Validate());
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}
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bool Validate() const
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{
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if(type == kNull)
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return true;
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if(!(1 <= level && level <= maxLevels))
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return false;
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if(entrySize == 0)
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if(type == kNull)
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return false;
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if(numEntries == 0) // disabled
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{
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if(entrySize != 0)
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return false;
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if(associativity != 0)
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return false;
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if(sharedBy != 0)
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return false;
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}
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else
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{
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if(entrySize == 0)
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return false;
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if(associativity == 0 || associativity > fullyAssociative)
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return false;
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if(sharedBy == 0)
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return false;
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}
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return true;
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}
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@ -67,33 +115,6 @@ struct x86_x64_Cache // POD (may be used before static constructors)
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{
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return u64(numEntries)*entrySize;
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}
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/**
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* if kNull, all other values are invalid.
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**/
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Type type;
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/**
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* 1..maxLevels
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**/
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size_t level;
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/**
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* = fullyAssociative or the actual ways of associativity
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**/
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size_t associativity;
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/**
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* NB: cache entries are lines, TLB entries are pages
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**/
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size_t entrySize;
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/**
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* how many logical processors share this cache?
|
||||
**/
|
||||
size_t sharedBy;
|
||||
|
||||
size_t numEntries;
|
||||
};
|
||||
|
||||
enum IdxCache
|
||||
@ -110,7 +131,7 @@ enum IdxCache
|
||||
|
||||
/**
|
||||
* @return 0 if idxCache >= TLB+numTLBs, otherwise a valid pointer to
|
||||
* a Cache whose type is null if not present.
|
||||
* a Cache whose numEntries is 0 if disabled / not present.
|
||||
**/
|
||||
LIB_API const x86_x64_Cache* x86_x64_Caches(size_t idxCache);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user