janwas
be3f3bdbfb
further cleanup to sysdep.h: avoid pulling in win and ia32; split header up into stl, compiler, and the actual sys_* API. (all but the latter are in PCH). timer: also avoid dragging in ia32 win: move snprintf fix to posix.h cpu: simplify reasoning about cores, now given as logicalPerCore (not package) vfs_optimizer: fix if archive building is partially disabled This was SVN commit r5008.
138 lines
3.7 KiB
C
138 lines
3.7 KiB
C
/**
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* =========================================================================
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* File : ia32.h
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* Project : 0 A.D.
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* Description : C++ and inline asm implementations for IA-32.
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*
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* @author Jan.Wassenberg@stud.uni-karlsruhe.de
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* =========================================================================
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*/
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/*
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* Copyright (c) 2003-2005 Jan Wassenberg
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*
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* Redistribution and/or modification are also permitted under the
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* terms of the GNU General Public License as published by the
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* Free Software Foundation (version 2 or later, at your option).
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*/
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#ifndef IA32_H
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#define IA32_H
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#if !CPU_IA32
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#error "including ia32.h without CPU_IA32=1"
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#endif
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#include "ia32_asm.h"
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#include "ia32_memcpy.h"
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// call before any of the following functions
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extern void ia32_init();
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// fpclassify return values
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#define IA32_FP_NAN 0x0100
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#define IA32_FP_NORMAL 0x0400
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#define IA32_FP_INFINITE (IA32_FP_NAN | IA32_FP_NORMAL)
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#define IA32_FP_ZERO 0x4000
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#define IA32_FP_SUBNORMAL (IA32_FP_NORMAL | IA32_FP_ZERO)
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// FPU control word
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// .. Precision Control:
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#define IA32_MCW_PC 0x0300
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#define IA32_PC_24 0x0000
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// .. Rounding Control:
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#define IA32_MCW_RC 0x0C00
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#define IA32_RC_NEAR 0x0000
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#define IA32_RC_DOWN 0x0400
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#define IA32_RC_UP 0x0800
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#define IA32_RC_CHOP 0x0C00
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// .. Exception Mask:
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#define IA32_MCW_EM 0x003f
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#define IA32_EM_INVALID BIT(0)
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#define IA32_EM_DENORMAL BIT(1)
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#define IA32_EM_ZERODIVIDE BIT(2)
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#define IA32_EM_OVERFLOW BIT(3)
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#define IA32_EM_UNDERFLOW BIT(4)
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#define IA32_EM_INEXACT BIT(5)
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extern void ia32_mfence();
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extern void ia32_serialize();
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extern u64 ia32_rdtsc_safe(void);
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#if CONFIG_RETURN64_EDX_EAX
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# define ia32_rdtsc ia32_asm_rdtsc_edx_eax
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#else
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# define ia32_rdtsc ia32_rdtsc_safe
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#endif
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extern void ia32_debug_break(void);
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// order in which registers are stored in CPUID regs array
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// (do not change! brand string relies on this ordering)
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enum IA32Regs
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{
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EAX,
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EBX,
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ECX,
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EDX
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};
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// CPU capability flags (128 bits)
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// do not change the order!
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enum IA32Cap
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{
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// standard (ecx) - currently only defined by Intel
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IA32_CAP_SSE3 = 0+0, // Streaming SIMD Extensions 3
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IA32_CAP_EST = 0+7, // Enhanced Speedstep Technology
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// standard (edx)
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IA32_CAP_FPU = 32+0, // Floating Point Unit
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IA32_CAP_TSC = 32+4, // TimeStamp Counter
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IA32_CAP_CMOV = 32+15, // Conditional MOVe
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IA32_CAP_MMX = 32+23, // MultiMedia eXtensions
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IA32_CAP_SSE = 32+25, // Streaming SIMD Extensions
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IA32_CAP_SSE2 = 32+26, // Streaming SIMD Extensions 2
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IA32_CAP_HT = 32+28, // HyperThreading
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// extended (ecx)
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// extended (edx) - currently only defined by AMD
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IA32_CAP_AMD_MP = 96+19, // MultiProcessing capable; reserved on AMD64
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IA32_CAP_AMD_MMX_EXT = 96+22,
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IA32_CAP_AMD_3DNOW_PRO = 96+30,
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IA32_CAP_AMD_3DNOW = 96+31
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};
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// indicate if the CPU supports the indicated cap.
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extern bool ia32_cap(IA32Cap cap);
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// checks if there is an IA-32 CALL instruction right before ret_addr.
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// returns INFO::OK if so and ERR::FAIL if not.
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// also attempts to determine the call target. if that is possible
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// (directly addressed relative or indirect jumps), it is stored in
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// target, which is otherwise 0.
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//
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// this is useful for walking the stack manually.
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extern LibError ia32_get_call_target(void* ret_addr, void** target);
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extern const char* ia32_identifierString();
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extern int ia32_isThrottlingPossible();
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extern double ia32_clockFrequency();
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extern uint ia32_numPackages();
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extern uint ia32_coresPerPackage();
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extern uint ia32_logicalPerCore();
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#endif // #ifndef IA32_H
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