forked from 0ad/0ad
janwas
f331b7313d
mahaf: now disabled on Win2k because we can't prevent the TLB bug there. removed the CopyPhysical API. wutil: allow querying windows version via number View: fix warning This was SVN commit r5169.
156 lines
4.4 KiB
C++
156 lines
4.4 KiB
C++
/**
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* =========================================================================
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* File : tsc.cpp
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* Project : 0 A.D.
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* Description : Timer implementation using RDTSC
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* =========================================================================
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*/
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// license: GPL; see lib/license.txt
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#include "precompiled.h"
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#include "tsc.h"
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#include "lib/sysdep/win/win.h"
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#include "lib/sysdep/win/wcpu.h"
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#include "lib/sysdep/ia32/ia32.h" // ia32_rdtsc
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#include "lib/bits.h"
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//-----------------------------------------------------------------------------
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// detect throttling
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enum AmdPowerNowFlags
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{
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PN_FREQ_ID_CTRL = BIT(1),
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PN_SW_THERMAL_CTRL = BIT(5),
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PN_INVARIANT_TSC = BIT(8)
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};
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static bool IsThrottlingPossible()
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{
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u32 regs[4];
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switch(ia32_Vendor())
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{
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case IA32_VENDOR_INTEL:
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if(ia32_cap(IA32_CAP_TM_SCC) || ia32_cap(IA32_CAP_EST))
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return true;
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break;
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case IA32_VENDOR_AMD:
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if(ia32_asm_cpuid(0x80000007, regs))
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{
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if(regs[EDX] & (PN_FREQ_ID_CTRL|PN_SW_THERMAL_CTRL))
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return true;
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}
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break;
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}
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return false;
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}
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//-----------------------------------------------------------------------------
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LibError CounterTSC::Activate()
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{
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ia32_Init();
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if(!ia32_cap(IA32_CAP_TSC))
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return ERR::NO_SYS; // NOWARN (CPU doesn't support RDTSC)
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return INFO::OK;
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}
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void CounterTSC::Shutdown()
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{
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ia32_Shutdown();
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}
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bool CounterTSC::IsSafe() const
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{
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// use of the TSC for timing is subject to a litany of potential problems:
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// - separate, unsynchronized counters with offset and drift;
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// - frequency changes (P-state transitions and STPCLK throttling);
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// - failure to increment in C3 and C4 deep-sleep states.
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// we will discuss the specifics below.
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// SMP or multi-core => counters are unsynchronized. this could be
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// solved by maintaining separate per-core counter states, but that
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// requires atomic reads of the TSC and the current processor number.
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//
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// (otherwise, we have a subtle race condition: if preempted while
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// reading the time and rescheduled on a different core, incorrect
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// results may be returned, which would be unacceptable.)
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//
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// unfortunately this isn't possible without OS support or the
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// as yet unavailable RDTSCP instruction => unsafe.
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//
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// (note: if the TSC is invariant, drift is no longer a concern.
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// we could synchronize the TSC MSRs during initialization and avoid
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// per-core counter state and the abovementioned race condition.
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// however, we won't bother, since such platforms aren't yet widespread
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// and would surely support the nice and safe HPET, anyway)
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if(ia32_NumPackages() != 1 || ia32_CoresPerPackage() != 1)
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return false;
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// recent CPU:
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if(ia32_Generation() >= 7)
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{
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// note: 8th generation CPUs support C1-clock ramping, which causes
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// drift on multi-core systems, but those were excluded above.
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u32 regs[4];
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if(ia32_asm_cpuid(0x80000007, regs))
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{
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// TSC is invariant WRT P-state, C-state and STPCLK => safe.
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if(regs[EDX] & PN_INVARIANT_TSC)
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return true;
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}
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// in addition to P-state transitions, we're also subject to
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// STPCLK throttling. this happens when the chipset thinks the
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// system is dangerously overheated; the OS isn't even notified.
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// it may be rare, but could cause incorrect results => unsafe.
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return false;
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// newer systems also support the C3 Deep Sleep state, in which
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// the TSC isn't incremented. that's not nice, but irrelevant
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// since STPCLK dooms the TSC on those systems anyway.
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}
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// we're dealing with a single older CPU; the only problem there is
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// throttling, i.e. changes to the TSC frequency. we don't want to
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// disable this because it may be important for cooling. the OS
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// initiates changes but doesn't notify us; jumps are too frequent
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// and drastic to detect and account for => unsafe.
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if(IsThrottlingPossible())
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return false;
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return true;
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}
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u64 CounterTSC::Counter() const
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{
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return ia32_rdtsc();
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}
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/**
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* WHRT uses this to ensure the counter (running at nominal frequency)
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* doesn't overflow more than once during CALIBRATION_INTERVAL_MS.
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**/
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uint CounterTSC::CounterBits() const
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{
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return 64;
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}
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/**
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* initial measurement of the tick rate. not necessarily correct
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* (e.g. when using TSC: wcpu_ClockFrequency isn't exact).
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**/
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double CounterTSC::NominalFrequency() const
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{
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return wcpu_ClockFrequency();
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}
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