lib: add CPU error code.
ia32: replace get_cur_processor_id with cpuid(0); move cpuid(func, regs) to asm - it takes care of detecting cpuid. This was SVN commit r2710.
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@ -270,6 +270,8 @@ enum LibError
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WARN_TEX_INVALID_DATA = +1505,
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ERR_TEX_INVALID_SIZE = -1506,
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ERR_CPU_FEATURE_MISSING = -1600,
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ERR_LAST
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};
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@ -56,6 +56,8 @@ extern void serialize();
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# define SP_ Esp
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#endif
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// internal use only
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extern bool cpuid(u32 func, u32* regs);
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#ifdef __cplusplus
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}
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@ -1,8 +1,10 @@
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section .text use32
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CACHEBLOCK equ 128
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BP_MIN_THRESHOLD_64 equ 192*1024
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MOVNTQ_MIN_THRESHOLD_64 equ 64*1024
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section .text
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%macro MC_UNROLLED_MOVSD 0
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and ebx, 63
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@ -219,32 +221,84 @@ _movntq:
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[section .data use32]
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cpuid_available dd -1
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; max supported CPUID functions. initialized to
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max_func dd 0x7FFFFFFF
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max_ext_func dd 0xFFFFFFFF
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__SECT__
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; extern "C" bool __cdecl cpuid(u32 func, u32* regs)
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global _cpuid
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_cpuid:
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; if unknown, detect; if not available, fail.
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xor eax, eax ; return val on failure
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cmp [cpuid_available], eax
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jl .one_time_init
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je .ret
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; extern "C" int __cdecl get_cur_processor_id();
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global _get_cur_processor_id
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_get_cur_processor_id:
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push ebx
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push 1
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pop eax
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push edi
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mov ecx, [esp+8+4+0] ; func
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mov edi, [esp+8+4+4] ; -> regs
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; compare against max supported func and fail if above
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test ecx, ecx
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mov edx, [max_ext_func]
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js .is_ext_func
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mov edx, [max_func]
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.is_ext_func:
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cmp ecx, edx
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ja .ret
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; issue CPUID and store result registers in array
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mov eax, ecx
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cpuid
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shr ebx, 24
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mov eax, ebx ; ebx[31:24]
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stosd
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xchg eax, ebx
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stosd
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xchg eax, ecx
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stosd
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xchg eax, edx
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stosd
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; success
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xor eax, eax
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inc eax
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.ret:
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pop edi
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pop ebx
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ret
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.one_time_init:
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; check if CPUID is supported
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pushfd
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or byte [esp+2], 32
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popfd
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pushfd
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pop eax
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xor edx, edx
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shr eax, 22 ; bit 21 toggled?
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adc edx, 0
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mov [cpuid_available], edx
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; determine max supported function
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xor eax, eax
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cpuid
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mov [max_func], eax
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mov eax, 0x80000000
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cpuid
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mov [max_ext_func], eax
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jmp _cpuid ; now try again
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@ -232,20 +232,19 @@ void serialize()
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static char vendor_str[13];
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static int family, model, ext_family;
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// used in manual cpu_type detect
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static u32 max_ext_func;
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static int num_cores;
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// caps
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// treated as 128 bit field; order: std ecx, std edx, ext ecx, ext edx
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// keep in sync with enum CpuCap and cpuid() code!
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u32 caps[4];
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static int have_brand_string = 0;
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// if false, need to detect cpu_type manually.
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// int instead of bool for easier setting from asm
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static bool have_brand_string; // if false, need to detect cpu_type manually.
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// order in which registers are stored in regs array
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enum Regs
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// (do not change! brand string relies on this ordering)
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enum IA32Regs
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{
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EAX,
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EBX,
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@ -259,184 +258,52 @@ enum MiscCpuCapBits
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POWERNOW_FREQ_ID_CTRL = 2
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};
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static bool cpuid(u32 func, u32* regs)
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{
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if(func > max_ext_func)
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return false;
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// (optimized for size)
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#if HAVE_MS_ASM
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__asm
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{
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mov eax, [func]
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cpuid
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mov edi, [regs]
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stosd
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xchg eax, ebx
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stosd
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xchg eax, ecx
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stosd
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xchg eax, edx
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stosd
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}
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#elif HAVE_GNU_ASM
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asm("cpuid"
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: "=a" (regs[0]),
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"=b" (regs[1]),
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"=c" (regs[2]),
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"=d" (regs[3])
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: "a" (func));
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#endif
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return true;
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}
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#if HAVE_MS_ASM
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// (optimized for size)
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static void cpuid()
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{
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__asm
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{
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pushad ;// save ebx, esi, edi, ebp
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;// ICC7: pusha is the 16-bit form!
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;// make sure CPUID is supported
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pushfd
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or byte ptr [esp+2], 32
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popfd
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pushfd
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pop eax
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shr eax, 22 ;// bit 21 toggled?
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jnc no_cpuid
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;// get vendor string
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xor eax, eax
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cpuid
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mov edi, offset vendor_str
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xchg eax, ebx
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stosd
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xchg eax, edx
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stosd
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xchg eax, ecx
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stosd
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;// (already 0 terminated)
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;// get CPU signature and std feature bits
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push 1
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pop eax
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cpuid
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mov [caps+0], ecx
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mov [caps+4], edx
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movzx edx, al
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shr edx, 4
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mov [model], edx ;// eax[7:4]
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movzx edx, ah
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and edx, 0x0f
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mov [family], edx ;// eax[11:8]
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shr eax, 20
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and eax, 0x0f
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mov [ext_family], eax ;// eax[23:20]
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;// make sure CPUID ext functions are supported
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mov esi, 0x80000000
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mov eax, esi
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cpuid
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mov [max_ext_func], eax
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cmp eax, esi ;// max ext <= 0x80000000?
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jbe no_ext_funcs ;// yes - no ext funcs at all
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lea esi, [esi+4] ;// esi = 0x80000004
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cmp eax, esi ;// max ext < 0x80000004?
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jb no_brand_str ;// yes - brand string not available, skip
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;// get CPU brand string (>= Athlon XP, P4)
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mov edi, offset cpu_type
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push -2
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pop esi ;// loop counter: [-2, 0]
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$1: lea eax, [0x80000004+esi] ;// 0x80000002 .. 4
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cpuid
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stosd
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xchg eax, ebx
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stosd
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xchg eax, ecx
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stosd
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xchg eax, edx
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stosd
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inc esi
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jle $1
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;// (already 0 terminated)
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mov [have_brand_string], esi ;// esi = 1 = true
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no_brand_str:
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;// get extended feature flags
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mov eax, 0x80000001
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cpuid
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mov [caps+8], ecx
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mov [caps+12], edx
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no_ext_funcs:
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no_cpuid:
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popad
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} // __asm
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} // cpuid()
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#elif HAVE_GNU_ASM
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// optimized for readability ;-)
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static void cpuid()
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static int retrieve_cpuid_info()
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{
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u32 regs[4];
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u32 flags;
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/*
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Try to set bit 21 in flags, and check if the cpu implemented the
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*/
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asm("pushfl; "
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"orb $32, 2(%%esp); " /* bit 16+5 = 21 */
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"popfl; "
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"pushfl; "
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"popl %%eax; "
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: "=a" (flags));
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if (!(flags & (1<<21))) // bit 21 reset? don't have cpuid -> abort
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return;
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// vendor string
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// notes:
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// - vendor_str is already 0-terminated because it's static.
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// - 'strange' ebx,edx,ecx reg order is due to ModR/M encoding order.
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if(!cpuid(0, regs))
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return ERR_CPU_FEATURE_MISSING; // we need CPUID, i.e. Pentium+
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u32* vendor_str_u32 = (u32*)vendor_str;
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vendor_str_u32[0] = regs[EBX];
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vendor_str_u32[1] = regs[EDX];
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vendor_str_u32[2] = regs[ECX];
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// weird register ordering for vendor string (12 chars in b/d/cx)
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// eax is ignored here
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asm("xorl %%eax, %%eax; cpuid"
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: "=b" (((u32 *)vendor_str)[0]),
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"=d" (((u32 *)vendor_str)[1]),
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"=c" (((u32 *)vendor_str)[2])
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:
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: "eax");
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cpuid(1, regs);
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memcpy(caps, ®s[2], 8);
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model = (regs[0] & 0xff) >> 4; // eax[7:4]
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family = (regs[0] & 0xf00) >> 8; // eax[11:8]
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ext_family = (regs[0] & 0xf000) >> 20; // eax[23:20]
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cpuid(0x80000000, regs);
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max_ext_func=regs[0];
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if (max_ext_func < 0x80000000)
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return; /* no ext functions - skip remaining tests */
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if (max_ext_func >= 0x80000004)
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// processor signature, feature flags
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// (note: HT/SMP query is nontrivial and done below)
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if(!cpuid(1, regs))
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debug_warn("cpuid 1 failed");
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model = bits(regs[EAX], 4, 7);
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family = bits(regs[EAX], 8, 11);
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ext_family = bits(regs[EAX], 20, 23);
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caps[0] = regs[ECX];
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caps[1] = regs[EDX];
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// multicore count
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if(cpuid(4, regs))
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num_cores = bits(regs[EBX], 26, 31)+1;
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// extended feature flags
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if(cpuid(0x80000001, regs))
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{
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/* get brand string */
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cpuid(0x80000002, (u32*)cpu_type);
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cpuid(0x80000003, (u32*)(cpu_type+16));
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cpuid(0x80000004, (u32*)(cpu_type+32));
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have_brand_string = true;
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caps[2] = regs[ECX];
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caps[3] = regs[EDX];
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}
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cpuid(0x80000001, regs);
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memcpy(&caps[2], ®s[2], 8);
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} // cpuid()
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#endif
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// CPU brand string (AthlonXP/P4 or above)
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u32* cpu_type_u32 = (u32*)cpu_type;
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if(cpuid(0x80000002, cpu_type_u32+0 ) &&
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cpuid(0x80000003, cpu_type_u32+16) &&
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cpuid(0x80000004, cpu_type_u32+32))
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have_brand_string = true;
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return 0;
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}
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bool ia32_cap(CpuCap cap)
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@ -454,6 +321,7 @@ bool ia32_cap(CpuCap cap)
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// (for easier comparison)
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enum Vendor { UNKNOWN, INTEL, AMD };
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static Vendor vendor = UNKNOWN;
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@ -461,7 +329,6 @@ static Vendor vendor = UNKNOWN;
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static void get_cpu_type()
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{
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// note: cpu_type is guaranteed to hold 48+1 chars, since that's the
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@ -649,13 +516,12 @@ static void check_smp()
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if(!cpuid(1, regs))
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debug_warn("cpuid 1 failed");
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const uint log_cpus_per_package = bits(regs[EBX], 16, 23);
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// logical CPUs are initialized after one another =>
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// they have the same physical ID.
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// const int id = get_cur_processor_id();
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const int id = 0; // HACK: until build system can assemble .asm correctly
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const uint cur_id = bits(regs[EBX], 24, 31);
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const int phys_shift = ilog2(log_cpus_per_package);
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const int phys_id = id >> phys_shift;
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const int phys_id = cur_id >> phys_shift;
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// more than 1 physical CPU found
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static int last_phys_id = -1;
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@ -684,11 +550,8 @@ static void check_speedstep()
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void ia32_get_cpu_info()
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{
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cpuid();
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if(family == 0) // cpuid not supported - can't do the rest
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return;
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WARN_ERR_RETURN(retrieve_cpuid_info());
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// (for easier comparison)
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if(!strcmp(vendor_str, "AuthenticAMD"))
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vendor = AMD;
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else if(!strcmp(vendor_str, "GenuineIntel"))
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