Itms/0ad
1
0
Fork 0
forked from 0ad/0ad
Code Pull Requests Activity

Adds L4 cache detection for some new Haswell CPUs, fixes #2074

Browse Source 
This was SVN commit r13736.
This commit is contained in:
historic_bruno 2013-08-21 23:18:35 +00:00
parent 3174d16256
commit 0a0bd83cf0
1 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
source/lib/sysdep/arch/x86_x64/cache.h
View File

@ -1,4 +1,4 @@
/* Copyright (c) 2011 Wildfire Games
/* Copyright (c) 2013 Wildfire Games
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
@ -37,7 +37,7 @@ struct Cache // POD (may be used before static constructors)
// note: further values are "reserved"
};
static const size_t maxLevels = 3;
static const size_t maxLevels = 4;
static const size_t fullyAssociative = 0xFF; // (CPUID.4 definition)
@ -125,9 +125,11 @@ enum IdxCache
L1D = 1,
L2D,
L3D,
L4D,
L1I,
L2I,
L3I,
L4I,
TLB
};